Field-effect transistor and manufacturing process thereof

ABSTRACT

A field-effect transistor includes a gate, a source and a drain; a semiconductor layer between the source and the drain; and a gate insulator between the gate and the semiconductor layer. The gate insulator comprises a first layer adjoining the semiconductor layer; and a second layer. The first layer is formed from an amorphous fluoropolymer having a first dielectric constant and a first thickness. The second layer has a second dielectric constant and a second thickness. The first dielectric constant is smaller than 3, the first thickness is smaller than 200 nm, the second dielectric constant is higher than 5, and the second thickness is smaller than 500 nm.

STATEMENT OF GOVERNMENT LICENSE RIGHTS

The inventors received partial funding support through the STC Programof the National Science Foundation under Agreement Number DMR-0120967and the Office of Naval Research through Contract Award NumberN00014-04-1-0120. The Federal Government has certain license rights inthis invention.

BACKGROUND

1. Field of the Invention

The present invention relates to a field-effect transistor, amanufacturing process thereof and a circuit comprising a plurality ofsuch transistors.

2. Description of the Related Art

Over the last several years, organic and mixed transition metal oxidesemiconductor channel based field-effect transistors (FETs) have beenextensively studied because they can potentially lead to low-endconsumer electronic applications that can be produced at a very low coston large areas, and on flexible or free-form substrates.

Two critical aspects for the realization of these technologies relateto: 1) the environmental and electrical stability of FETs; and 2) to itslow voltage operation. The most common sign of device degradationmanifests itself as a threshold voltage shift upon prolonged gate biasstress. Other changes that could arise under bias stress are an increasein the sub-threshold slope, reductions of the field-effect mobility, anincrease in the OFF current and/or hysteresis between subsequentmeasurements.

Emerging FET technologies such as those based on organic or transitionmetal oxide semiconductors suffer from electrical instabilities butoffer some advantages over Si-based technologies in that they can beprocessed at lower temperatures and potentially at a lower cost. In theliterature, several routes have been taken to improve the stability ofFETs and can be summarized as follows: 1) passivation of gatedielectric/semiconductor interface 2) variation of gate dielectricmaterials; 3) annealing at high temperatures; 4) variation of source anddrain metal electrodes. Among the wide variety of materials used as gatedielectric, fluoropolymers, such as CYTOP, have shown potential toproduce interfaces with organic semiconductors with very low trapdensities. WO03/052841 in the name of Avecia Ltd (hereby incorporated byreference in its entirety) discloses a process of manufacturing suchorganic field-effect transistors, where CYTOP has been used incombination with one or more further insulator layers. However, polymershave typically a very low dielectric constant. The latter in conjunctionwith a large thickness required to avoid large leakage currents, resultsin a low capacitance density. On the other hand, gate dielectrics withhigh capacitance can be achieved through the use of inorganic high-kdielectric materials. However, in general the performance of the knowndevices with a multi-layer dielectric in bias stress tests isunacceptable for many applications.

D. K. Hwang et al., “Top-Gate Organic Field-Effect Transistors with HighEnvironmental and Operational Stability,” Adv. Mater. 23, 1293-1298(2011); D. K. Hwang et al., “Flexible and stable solution-processedorganic field-effect transistors,” Organic Electronics, 12, 1108 (2011);and D. K. Hwang et al., “Hysteresis mechanisms of pentacene thin-filmtransistors with polymer/oxide bilayer gate dielectrics,” Appl. Phys.Lett. 92, 013304 (2008) are hereby incorporated by reference in theirentireties.

SUMMARY OF THE INVENTION

The object of the invention is to provide a FET having high electricalstability that at the same time can operate at low voltages. More inparticular the object of the invention is to provide a FET with animproved performance under continuous bias stress.

According to an embodiment of the invention there is provided afield-effect transistor comprising a gate, a source and a drain. Asemiconductor layer extends between said source and said drain, andthere is provided a gate insulator between the gate and thesemiconductor layer. The gate insulator comprises a first layer and asecond layer. The first layer has a first dielectric constant and afirst thickness and touches the semiconductor layer along an interface.The interface comprises a plurality of traps causing a first effect on acurrent between the drain and the source over time under continuous biasstress. The second layer has a second dielectric constant and a secondthickness and the second dielectric constant is higher than the firstdielectric constant. The second layer is arranged such that said seconddielectric constant increases over time under continuous bias stresscausing a second effect on the current between the drain and the sourceover time under continuous bias stress. The first and second thicknessand the first and second dielectric constant are such that said firsteffect compensates at least partly said second effect.

Applying a continuous bias stress means that a drain voltage and gatevoltage corresponding to the normal operation of a FET are applied for along period of time (e.g. one hour). For example for a typical DC biasstress test, the drain and gate voltage could be equal and a couple ofvolts higher than the threshold voltage of the FET.

According to an embodiment of the invention said first effect on thecurrent between the drain and the source over time under continuous biasstress consists in an increase of the current over time while saidsecond effect on the current between the drain and the source over timeunder continuous bias stress consists in a decrease of this current. Thefirst and second thickness and the first and second dielectric constantare such that the increase over time compensates at least partly thedecrease over time. In that way the variation of the current between thedrain and the source over time under continuous bias stress remainswithin a limited range. Preferably said variation is less than threepercent of the initial current when applying a continuous bias for 1hour.

According to an embodiment of the invention the variation of the currentbetween the drain and the source under continuous bias stress (whereinthe drain and gate voltage with respect to the source voltage are atleast 0.5V above the threshold voltage, i.e. |V_(G)|,|V_(D)|>|V_(th)|+0.5V) for 1 hour is less than 5 percent, preferablyless than 3 percent. More preferably this variation is less than 5percent, preferably less than 3 percent, for 2 hours.

According to an embodiment of the invention the first and secondthickness and the first and second dielectric constant are such that thevariation of the current between the source and the drain normalized tothe initial current at the end of a DC bias test of one hour (whereinthe drain and gate voltage with respect to the source voltage are atleast 0.5V above the threshold voltage, i.e. |V_(G)|,|V_(D)|>|V_(th)|+0.5V) is less than 0.03 per hour, preferably less than0.015 per hour.

According to a preferred embodiment of the invention the second layercomprises dipoles causing an increase of the second dielectric constantover time under continuous bias stress. In that way, by introducingdipoles in the second layer, the second effect can be influenced inorder to obtain an optimal compensation of the first and second effect.In a further embodiment the dipoles produce a change of polarizationwhich compensates for the threshold voltage shifts produced by trappingat the interface between the semiconductor layer and the first layer.The second layer can e.g. be an organic layer in which dipolar moleculeshave been introduced.

According to a preferred embodiment the second dielectric layer ischosen such that it changes its polarizability as the device is exposedlonger to a DC electrical bias, such that it compensates the changes inthreshold voltage produced by trapping at the interface between thesemiconductor layer and the first layer.

It is noted that the field-effect transistor of the invention can be atop gate transistor or a bottom gate transistor. Further the transistorcan be an n-channel, a p-channel or ambipolar transistor.

According to another embodiment the field-effect transistor comprises agate, a source, a drain, a semiconductor layer between said source andsaid drain and a gate insulator between said gate and said semiconductorlayer. The gate insulator comprises a first layer adjoining saidsemiconductor layer; and a second layer. The first layer having a firstthickness is formed from an amorphous fluoropolymer having a firstdielectric constant. The second layer has a second dielectric constantand a second thickness. The first dielectric constant is smaller than 3,and the first thickness being smaller than 200 nm. The second dielectricconstant is higher than 5 and the second thickness is smaller than 500nm. In a preferred embodiment the second thickness is smaller than 300nm. In another embodiment, the second thickness is less than 50 nm.

According to a preferred embodiment the first layer is formed from anamorphous fluoropolymer having a glass transition temperature above 80degrees Celsius. According to a preferred embodiment the second layer isformed from an inorganic material. With such a gate insulator highcapacitance density and low leakage currents can be achieved bycombining a fluoropolymer layer with an inorganic dielectric layer witha higher-k. Also, the interface between the fluoropolymer and thesemiconductor layer significantly reduces the interfacial trap density,reducing polar interactions at this interface. This typically leads tonegligible hysteresis effects. In a top gate geometry such a bi-layertypically also acts as a barrier coating that can significantly reducethe diffusion of oxygen and moisture into the semiconductor layers,therefore improving the overall FET stability. The combined propertiesoffered by this multilayer gate insulator can therefore be applied to avariety of semiconductor materials. Furthermore, this multilayer gatestructure serves as an efficient protection layer when the FETs aresubjected to extreme conditions such as oxygen plasma, and immersion inwater or common organic solvents, such as acetone. This will allow theuse of a photolithography process to pattern the metal gate.

According to an embodiment the first layer is formed of a copolymer offluorinated 1,3-dioxole and tetrafluoroethylene (TFE), having theformula:

An example thereof is a copolymer of4,5-difluoro-2,2-bis(trifluoromethyl)-1,3-dioxole (PDD) andtetrafluoroethylene (TFE) such as TEFLON AF with X: F; Y, Z: CF₃ and forexample TEFLON AF 1600 (65% mol PDD, Tg 160° C., permittivity 1.93) orAF 2400 (87% mol PDD, Tg 240° C., permittivity 1.90). Another example isa copolymer of 2,2,4-trifluoro-5-trifluoromethoxy-1,3-dioxole (TTD) andtetrafluoroethylene (TFE), such as HYFLON AD with X: OCF₃; Y, Z: F, andfor example HYFLON AD40 (40% mol in TDD, Tg 95° C.) or AD60 (60% mol inTDD, Tg 125° C.).

According to another embodiment the first layer is formed of analternating copolymer of perfluorofuran (PFF) and tetrafluoroethylene(TFE); or a homo- or copolymer of perfluoro(4-vinyloxyl)-1-alkenes, asshown in the formula below:

or a PFF derivative having the structure below:

Suitable commercially available materials of this type can be found inthe CYTOP class. An example is CYTOP grade CTL-809M supplied by AsahiGlass Corporation, Co. Ltd.

According to a preferred embodiment, the inorganic material of thesecond layer comprises any one of the following materials, or acombination thereof: Al₂O₃, SiN_(x), TiO₂, HfO₂, Ta₂O₅, SiO₂, Y₂O₃, ZrO₂or any other suitable material. A particularly preferred material isAl₂O₃. According to another embodiment the second layer is fabricatedfrom an organic material, and for example any one of the followingmaterials: polymers comprising a polymer matrix having a chargedistribution with orientable and/or inducible dipoles or a polymermatrix doped with molecules with permanent dipoles. The presence of suchpermanent or inducible dipoles will cause the dielectric constant of thesecond layer to vary over time under continuous bias stress as aconsequence of a varying electric field over the second layer. Hence, byan appropriate choice of materials with dipole behavior for the secondlayer, the above mentioned second effect can be reached.

According to a preferred embodiment the second layer is deposited by anyone of the following techniques: atomic layer deposition (ALD), electronbeam deposition, RF-sputtering, chemical vapor deposition (CVD orPECVD), pulsed-layer deposition (PLD), spin-coating, printing,lamination, doctor-blading or any other known suitable method. Aparticularly preferred technique is atomic layer deposition (ALD). Al₂O₃has a high relative dielectric constant and ALD makes it possible todeposit a very thin layer thereof. In that way a device can be obtainedwith a sufficiently high capacitance density allowing low voltageoperation.

According to a preferred embodiment the thickness of the first layer isless than 200 nm, preferably less than 100 nm, and more preferably lessthan 50 nm. According to a preferred embodiment the thickness of thesecond layer is less than 500 nm, preferably less than 100 nm, and morepreferably less than 50 nm. Typically, it is preferred to have a smallthickness, however guaranteeing a sufficiently low leakage current andan improved stability under continuous bias stress. More in particularthe choice of the thickness will typically depend on the interplaybetween the first and second thickness, and the first and seconddielectric constant and on the threshold voltage shift in function oftime under continuous bias stress that is produced at the interfacebetween the first layer and the semiconductor layer.

According to a preferred embodiment the gate insulator is a bi-layerconsisting of the first and second layer.

According to a preferred embodiment the gate insulator further comprisesa third layer between the second layer and the gate. In a bottom-gateFET, this third layer will typically be deposited on top of thesemiconductor layer to protect it from air. Such a third layer canfurther improve the barrier properties. The third layer can be formedfrom any barrier coating material such as an amorphous fluoropolymerwhich functions as a passivation layer for the underlying inorganicdielectric layer. The thickness of the third layer is preferably lessthan 100 nm, more preferably less than 50 nm, and most preferably lessthan 25 nm. For very specific applications, it is possible to use morethan three layers, but usually it is preferred to limit the thickness ofthe gate insulator.

According to a preferred embodiment the semiconductor layer is anorganic semiconductor layer, wherein the material of the first layer issoluble in an orthogonal solvent. Solvent orthogonality betweenfluoropolymers and commonly used organic semiconducting layers makes itpossible to spin coat on top of the organic channel layer in case of atop gate geometry. According to a preferred embodiment the semiconductorlayer is an organic semiconductor layer selected from any one of thefollowing materials: a pentacene layer, a blend oftriisopropylsilylethynyl (TIPS)-pentacene in polytriarylamine (PTAA), ora blend of 5,11-Bis(triethylsilylethynyl)anthradithiophene (diF-TESADT)in PTAA. According to another embodiment the semiconductor layer is aninorganic semiconductor layer, such as a transition metal oxide.

According to a preferred embodiment the second relative dielectricconstant is higher than 5, preferably higher than 7.

The invention further relates to a circuit, e.g. a backplane circuit fora display, an inverter circuit, a ring oscillator, a logic gate, etc,comprising a plurality of field effect transistors according to any oneof the embodiments disclosed above.

A further embodiment of the invention provides a process formanufacturing a top gate field-effect transistor comprising providing asource, a drain, a gate, a semiconductor layer between the source andthe drain, and a gate insulator between said gate and said semiconductorlayer. The providing of the gate insulator comprises depositing a firstlayer having a first dielectric constant and a first thickness. Thefirst layer defines an interface with the semiconductor layer. Thedepositing of the first layer and the providing of the semiconductorlayer is such that the interface comprises a plurality of traps causinga first effect on the drain source current over time under continuousbias stress. The providing of the gate insulator also comprisesdepositing a second layer having a second dielectric constant and asecond thickness, said second dielectric constant being higher than saidfirst dielectric constant and said second dielectric constant increasingover time under continuous bias stress causing a second effect on thedrain source current over time under continuous bias stress. The firstand second thickness and said first and second dielectric constant arechosen in such a way that the first effect compensates at least partlythe second effect.

According to a preferred embodiment of the process, the source and drainare patterned on a glass substrate and the semiconductor layer isdeposited on said glass substrate burying the source and the drain.

According to a preferred embodiment of the process, the gate insulatoris provided on top of a substrate and the semiconductor layer isdeposited on top of the gate insulator.

According to a preferred embodiment of the process, the first layer isdeposited by spin coating using a fluoro-solvent in combination with anamorphous fluoropolymer.

According to a preferred embodiment of the process, the second layer isdeposited by atomic layer deposition (ALD).

According to a preferred embodiment of the process, the providing of thegate insulator further comprises depositing a third layer of anamorphous fluoropolymer on top of said second layer.

In another embodiment, a composition is provided comprising at least oneelectron transport semiconductor and at least one polymer matrix. In oneembodiment, the electron transport organic semiconductor has a molecularweight of about 1,000 or less. In one embodiment, the polymer is a holetransporting material. In one embodiment, the polymer comprises anarylamine. In one embodiment, the polymer is an optionally substitutedpolystyrene, such as poly(α-methyl styrene). The amount of polymer canbe, for example 10 wt. % to 90 wt. %, and the amount of semiconductorcan be, for example, 10 wt. % to 90 wt. %.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are schematic section views of a top gate field-effecttransistor (FET) and of a bottom gate FET, respectively, according to afirst embodiment of the invention.

FIG. 2 is a schematic section view of a FET according to a secondembodiment of the invention.

FIG. 3 illustrate the first, second, and third effects influencing thedrain current under continuous bias stress in an embodiment of a FETaccording to the invention;

FIG. 4A shows a section view of a field-effect transistor with aCYTOP/Al₂O₃ dielectric; FIG. 4B shows a section view of a TIPS-pentaceneand Poly (triarylamine) (PTAA) blend channel based OFET with aCYTOP/Al₂O₃ bi-layer (40 nm CYTOP; 50 nm Al₂O₃) using a glass substrate;FIG. 4C shows a section view of a TIPS-pentacene and PTAA blend channelbased OFET with a CYTOP/Al₂O₃ bi-layer using a plastic substrate; FIG.4D shows a section view of a TIPS-pentacene and PTAA blend channel basedOFET with CYTOP/Al₂O₃ bi-layer (45 nm CYTOP; 50 nm Al₂O₃); FIG. 4E showsa section view of a diF-TESADT and PTAA blend channel based OFET with aCYTOP/Al₂O₃ bi-layer (45 nm CYTOP; 50 nm Al₂O₃); FIG. 4F shows a sectionview of a TIPS-pentacene and Poly PTAA blend channel based OFET with aCYTOP/Al₂O₃/CYTOP tri-layer (20 nm CYTOP; 50 nm Al₂O₃; 20 nm CYTOP);FIG. 4G shows a section view of a Pentacene and InGaZnO based inverters;and FIG. 4H shows a section view of a Polyera ActivInk N2200 based OFETwith a CYTOP/Al₂O₃ bi-layer (45 nm CYTOP; 50 nm Al₂O₃) and evaporated Agsource/drain electrodes.

FIG. 5 illustrates the ratio of the drain current I_(DS) with respect tothe initial drain current I_(DS0) in function of the time undercontinuous bias stress in the OFET of FIG. 4A for three different CYTOPlayer thicknesses.

FIGS. 6A and 6B illustrate the influence of the CYTOP layer thicknesst_(CYTOP) and of the Al₂O₃ dielectric constant k_(Al2O3) on the voltageV_(CYTOP) over the CYTOP layer and on the voltage V_(Al2O3) over theAl₂O₃ layer.

FIGS. 7A and 7B show the capacitance density-electric field (C-E) andcurrent density-electric field (J-E) characteristics of Al₂O₃ (100 nm),CYTOP (780 nm), and CYTOP (40 nm)/Al₂O₃ (50 nm) films, respectively.

FIGS. 8A and 8B show the transfer and output characteristics, measuredfor an OFET (W/L=2550 μm/180 μm) using a CYTOP (40 nm)/Al₂O₃ (50 nm)gate dielectric, respectively.

FIG. 9A shows a table that summarizes the different conditions ofenvironmental exposure and electrical stress to which sets of OFETs weresubjected; FIGS. 9B and 9C show the variations of the mobility and thethreshold voltage V_(th) in time, respectively, for OFETs with Al₂O₃(100 nm), CYTOP (780 nm), and CYTOP (40 nm)/Al₂O₃ (50 nm) films; andFIG. 9D shows the variations of the mobility and the threshold voltageV_(th) For an OFET with a CYTOP (40 nm)/Al₂O₃ (50 nm) film.

FIGS. 10A and 10B show a sampling of the transfer curves measured in aCYTOP (40 nm)/Al₂O₃ (50 nm) OFET during multiple continuous scans fromthe “off” to the “on” region, before and after air exposure.

FIGS. 11A, 11B and 11C shows the temporal evolution of the I_(DS)measured in different OFETs normalized to the initial value before airexposure, after air exposure for 31 days and after air exposure for 31days and O₂ plasma for 5 minutes, respectively; FIG. 11D shows atransfer and output characteristics before and after DC bias stress forthe device of FIG. 4A; and FIG. 11E shows the temporal evolution of theI_(DS) over 24 h of electrical bias stress measured in an OFET with aCYTOP (40 nm)/Al₂O₃ (50 nm) film under various conditions.

FIGS. 12A and 12B show the transfer and output characteristics ofamorphous InGaZnO FETs with the CYTOP/Al₂O₃ bi-layer after multiplescans of the transfer characteristic and after a constant DC bias stressfor 18 hour, respectively.

FIGS. 13A-13B show the transfer and output characteristics, measuredfrom pristine devices under a nitrogen atmosphere, of OFETs (W/L=2550μm/180 μm) using a CYTOP (40 nm)/Al₂O₃ (50 nm) gate dielectric and aplastic (PES) substrate.

FIG. 14A shows the temporal evolution of the I_(DS) during DC biasstress measured in OFETs (W/L=2550 μm/180 μm) using a CYTOP (40nm)/Al₂O₃ (50 nm) gate dielectric and a plastic (PES) substrate,normalized to the initial value. FIGS. 14B and 14C show the transfer andoutput characteristics of the plastic substrate OFET after beingsubjected to the DC bias stress.

FIGS. 15A and 15B show the transfer and output characteristics of OFETs(W/L=2550 μm/180 μm) using a CYTOP (40 nm)/Al₂O₃ (50 nm) gate dielectricand a plastic (PES) substrate initially, after 4 months in air, andafter bending for 30 minutes (tensile stress). FIG. 15C shows thebending apparatus used to bend the plastic substrate OFET. FIG. 15Dshows the voltage transfer characteristics of a resistive-load inverterswith the plastic substrate OFET initially, after 2 hours of DC biasstress, after 4 months in air, and after bending for 30 minutes (tensilestress).

FIG. 16A-16C illustrate O₂ and H₂O effects on threshold voltage shift inthe transfer characteristics of OFETs (FIGS. 16A and 16B) and thevariation of drain current under constant dc bias stress (FIG. 16C)

FIG. 17 illustrates an exposure sequence showing the conditions to whichsets of OFETs were exposed to determine their environmental stability.

FIGS. 18A-18C show the capacitance C_(in)(nF/cm²), mobility μ(cm²/Vs),and threshold voltage V_(th)(V) for each stage of the exposure sequenceof FIG. 17.

FIGS. 19A and 19B show the variation in capacitance for frequenciesranging from 20 Hz to 1 million Hz, for the CYTOP/Al₂O₃ bi-layer OFET(45 nm CYTOP; 50 nm Al₂O₃) (FIG. 19A) and the CYTOP/Al₂O₃/CYTOPtri-layer OFET (20 nm CYTOP; 50 nm Al₂O₃; 20 nm CYTOP) (FIG. 19B), ateach stage of the exposure sequence of FIG. 17.

FIGS. 20A and 20B show the transfer characteristics and temporalevolution of the I_(DS) during DC bias for a TIPS-pentacene and PTAAblend channel based OFET with a CYTOP/Al₂O₃ bi-layer (45 nm CYTOP; 50 nmAl₂O₃), after each stage of the exposure sequence of FIG. 17.

FIGS. 21A and 21B show the transfer characteristics and temporalevolution of the I_(DS) during DC bias for a diF-TESADT and PTAA blendchannel based OFET with a CYTOP/Al₂O₃ bi-layer (45 nm CYTOP; 50 nmAl₂O₃), after each stage of the exposure sequence of FIG. 17.

FIGS. 22A and 22B show the transfer characteristics and temporalevolution of the I_(DS) during DC bias for a TIPS-pentacene and PTAAblend channel based OFET with a CYTOP/Al₂O₃/CYTOP tri-layer (20 nmCYTOP; 50 nm Al₂O₃; 20 nm CYTOP), after each stage of the exposuresequence of FIG. 17.

FIGS. 23A-23D show the capacitance and current density-electric field(J-E) characteristics of capacitors with varying fluoropolymerbi-layers.

FIGS. 24A and 24B show the transfer characteristic and outputcharacteristics for a CYTOP (45 nm)/Al₂O₃ (50 nm) bi-layer OFET. FIGS.24C and 24D show the transfer characteristic and output characteristicsfor a Hyflon (45 nm)/Al₂O₃ (50 nm) bi-layer OFET. FIGS. 24E and 24F showthe transfer characteristic and output characteristics for a Teflon (45nm)/Al₂O₃ (50 nm) bi-layer OFET. FIGS. 24G and 24H show the transfercharacteristic and output characteristics for a CYTOP (20 nm)/Al₂O₃ (50nm)/CYTOP (20 nm) tri-layer OFET. FIGS. 24I and 24J show the transfercharacteristic and output characteristics for a CYTOP (45 nm)/S_(i)N_(x)(50 nm) bi-layer OFET. FIGS. 24K and 24L show the transfercharacteristic and output characteristics for a Hyflon (45nm)/S_(i)N_(x) (50 nm) bi-layer OFET. FIGS. 24M and 24N show thetransfer characteristic and output characteristics for a Teflon (45nm)/S_(i)N_(x) (50 nm) bi-layer OFET. FIGS. 24O and 24P show thetransfer characteristic and output characteristics for a CYTOP (20nm)/S_(i)N_(x) (50 nm)/CYTOP (20 nm) tri-layer OFET.

FIGS. 25A and 25B show the drain current I_(DS) with respect to gatevoltage V_(GS) for the pentacene and InGaZnO FETs of FIG. 4G after 500consecutive sweeps.

FIG. 25C shows the temporal evolution of the I_(DS) measured in thepentacene and InGaZnO FETs, normalized to the initial value, under DCbias stress over 60 minutes.

FIGS. 26A and 26B show the transfer characteristics and outputcharacteristics of the pentacene FETs of FIG. 4G after various stressconditions.

FIGS. 27A and 27B show the transfer characteristics and outputcharacteristics of the InGaZnO FETs of FIG. 4G after various stressconditions.

FIGS. 28A and 28B show the voltage transfer characteristics and staticgain of the inverter of FIG. 4G after various stress conditions.

FIGS. 29A and 29B show the transfer characteristics and outputcharacteristics of a Polyera ActivInk N2200 based OFET with aCYTOP/Al₂O₃ bi-layer (45 nm CYTOP; 50 nm Al₂O₃) and evaporated Ausource/drain electrodes, as discussed in Example 12.

FIGS. 30A and 30B show the transfer characteristics and outputcharacteristics of a Polyera ActivInk N2200 based OFET with aCYTOP/Al₂O₃ bi-layer (45 nm CYTOP; 50 nm Al₂O₃) and evaporated Agsource/drain electrodes, as discussed in Example 13.

FIGS. 31A and 31B show the transfer characteristics and outputcharacteristics of a Polyera ActivInk N2200 based OFET with aCYTOP/Al₂O₃ bi-layer (45 nm CYTOP; 50 nm Al₂O₃) and printed Agsource/drain electrodes, as discussed in Example 14.

FIGS. 32A and 32B show the transfer characteristics and outputcharacteristics of an LEH-III-002a based OFET with a CYTOP/Al₂O₃bi-layer (45 nm CYTOP; 50 nm Al₂O₃) and Au bottom contact source/drainelectrodes in n-mode operation.

FIGS. 33A and 33B show the transfer characteristics and outputcharacteristics of an LEH-III-002a based OFET with a CYTOP/Al₂O₃bi-layer (45 nm CYTOP; 50 nm Al₂O₃) and Au bottom contact source/drainelectrodes in p-mode operation.

FIGS. 34A and 34B show the transfer characteristics and outputcharacteristics of an LEH-III-085g based OFET with a CYTOP/Al₂O₃bi-layer (45 nm CYTOP; 50 nm Al₂O₃) and Al bottom contact source/drainelectrodes.

FIGS. 35A and 35B show the transfer characteristics and outputcharacteristics of an LEH-III-085g:PαMS based OFET with a CYTOP/Al₂O₃bi-layer (45 nm CYTOP; 50 nm Al₂O₃) and Ag bottom contact source/drainelectrodes in n-mode operation.

FIGS. 36A and 36B show the transfer characteristics and outputcharacteristics of an LEH-III-085g:PαMS based OFET with a CYTOP/Al₂O₃bi-layer (45 nm CYTOP; 50 nm Al₂O₃) and Ag bottom contact source/drainelectrodes in p-mode operation.

FIGS. 37A and 37B show the results of an ambient exposure study on theLEH-III-119a based OFET with a CYTOP/Al₂O₃ bi-layer (45 nm CYTOP; 50 nmAl₂O₃) and Au bottom contact source/drain electrodes.

FIGS. 38A and 38B show the results of an ambient exposure study on theLEH-III-119a/PαMS blend based OFET with a CYTOP/Al₂O₃ bi-layer (45 nmCYTOP; 50 nm Al₂O₃) and Au bottom contact source/drain electrodes.

FIGS. 39A and 39B show the transfer characteristics and outputcharacteristics of a DRR-IV-209n based OFET with a CYTOP/Al₂O₃ bi-layer(45 nm CYTOP; 50 nm Al₂O₃).

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1A illustrates a first embodiment of a top gate field-effecttransistor (FET) according to the invention. The illustrated FETembodiment comprises a substrate 101, a semiconductor layer 102, asource and a drain 109 buried or in contact with in the semiconductorlayer, a gate insulator 103, 104 on top of the semiconductor layer 102,and a gate 110 on top of the gate insulator. The gate insulatorcomprises a first layer 103 formed from a first material, e.g. anamorphous fluoropolymer and a second layer 104 formed from a seconddielectric material, typically a high-k dielectric. The source and drainelectrode 109 are typically patterned on the substrate 101, and thelayer of semiconductor material 102 is deposited over the source anddrain electrodes 109. Note that the top gate structure could bestaggered (as illustrated in FIG. 1A) or coplanar where the source anddrain 109 touch the gate insulator layer 103. The top gate metalelectrode 110 is typically patterned on the second layer 104. FIG. 1Billustrates a similar embodiment for a bottom gate FET with a substrate101′, a gate 110′, a bi-layer gate dielectric 103′,104′, a semiconductorlayer 102′ and a drain and source 109′.

The thickness of the first layer 103, 103′ is preferably less than 200nm, more preferably less than 100 nm, and most preferably less than 50nm. Further, preferably the thickness of the second layer 104, 104′ isless than 500 nm, more preferably less than 100 nm, and most preferablyless than 50 nm.

The use of an amorphous fluoropolymer/high-k oxide bi-layer combines thegood chemical properties of amorphous fluoropolymer with the high filmquality and large capacitance density of high-k oxides. In addition, forthe top gate geometry, this bi-layer gate dielectric also has betterencapsulation properties against environmental exposure than a singlelayer amorphous fluoropolymer.

The material of the first layer can e.g. be any one of the followingmaterials: a copolymer of fluorinated 1,3-dioxole andtetrafluoroethylene (TFE), such as a copolymer of4,5-difluoro-2,2-bis(trifluoromethyl)-1,3-dioxole (PDD) andtetrafluoroethylene (TFE) or a copolymer of2,2,4-trifluoro-5-trifluoromethoxy-1,3-dioxole (TTD) andtetrafluoroethylene (TFE); a copolymer of perfluorofuran (PFF) andtetrafluoroethylene (TFE); a homo- or copolymer ofperfluoro(4-vinyloxyl)-1-alkenes. The first layer can e.g. be depositedfrom a formulation with the fluoropolymer and one or morefluoro-solvents by any one of the following printing or coatingtechniques: spin coating, doctor blading, wire bar coating, spray or dipcoating, ink jet printing, gravure printing, flexo printing, or anyother known suitable method.

The dielectric material of the second layer is preferably a high-kinorganic dielectric, and can e.g. be any one of the followingmaterials: Al₂O₃, SiN_(X), TiO₂, HfO₂, Ta₂O₅, SiO₂, Y₂O₃, ZrO₂, anyother suitable materials. Alternatively the second layer can be formedfrom an organic material, and for example any one of the followingmaterials: polymers comprising orientable and/or inducible dipoles or apolymer matrix doped with molecules with permanent dipoles. The secondlayer can e.g. be deposited by any one of the following techniques:atomic layer deposition (ALD), electron beam deposition, RF-sputteringor plasma-enhanced chemical vapor deposition, pulsed laser deposition(PLD), or any other known suitable technique. According to a preferredembodiment the second layer is an Al₂O₃ layer deposited by ALD.

The semiconductor layer can be either an organic or an inorganicsemiconductor layer. An example of an organic layer is a TIPS-pentaceneand Poly (triarylamine) (PTAA) layer, a pentacene layer, a rubrenelayer, a TIPS-pentacene and PCBMC₆₀ layer. Such a layer may e.g. beapplied by spin-coating or any suitable printing or coating technique,by physical vapor deposition, by organic vapor phase deposition, or anyother known vacuum deposition method. An example of an inorganic layeris a transition metal oxide such as an InGaZnO, ZnO, InZnO, GaZnO,In₂O₃, or any other know suitable semiconductor including amorphoussilicon and poly-silicon.

The substrate 101 is typically a rigid or flexible substrate such asrigid glass, flexible glass, Si wafer, PET, PES, PEN, Polyimide, metalfoil substrates.

Such a gate dielectric is intended to provide a change of polarizabilityunder a continuous DC bias that compensates the change in the thresholdvoltage produced by trapping at the semiconductor layer 102, 102′ or atthe interface between the semiconductor layer and the first layer 103,103′, improving the electrical stability. This is illustrated in FIG. 3.The instability mechanisms that influence the drain source current in aFET with a bi-layer dielectric are amongst others:

-   -   the interfacial (shallow or deep) traps at the interface between        the semiconductor layer and the first layer;    -   gate charge injection at the interface between the gate        electrode and the gate dielectric;    -   dipole polarization or mobile impurity moving in the second        layer;    -   the bulk traps inside the semiconductor layer.

The interfacial traps (first effect), gate charge injection (secondeffect), and dipole polarization (third effect) play a major role on thedrain source current in function of time under continuous bias stress,see FIG. 3. The first effect causes a decrease of the current while thesecond and third effects cause an increase of the current. According toan embodiment of the invention the thicknesses t1 and t2 of the firstand second layer and the dielectric constants k1 and k2 are chosen suchthat those effects at least partially compensate each other, see thecurrent curve drawn in a full line in FIG. 3.

FIG. 2 illustrates a second embodiment of a FET according to theinvention which is similar to the first embodiment (the elements101-104, 109, 110 correspond with the elements 201-204, 209, 210) withthis difference that a third layer 205 is added above the second layer.The third layer 205 is preferably formed of an amorphous fluoropolymer.Such a third layer forms a passivation layer for the underlyinginorganic dielectric layer 204 which can lead to a better long termstability. The thickness of the third layer 205 is preferably less than100 nm, more preferably less than 50 nm, and most preferably less than25 nm. This thickness can be further optimized to further improve theabove described compensation effect. Note however that it is usuallypreferred to keep the gate insulator as thin as possible, and thestability of the bi-layer gate insulator illustrated in FIG. 1A willtypically provide sufficient stability.

Example 1 TIPS-Pentacene and Poly (Triarylamine) (PTAA) Blend ChannelBased OFET with CYTOP/Al₂O₃ Bi-Layer Using Glass Substrate (40 nm CYTOP;50 nm Al₂O₃)

OFETs with a bottom-contact and top-gate structure were fabricated onglass substrates (Corning 1737). Poly-4-vinylphenol (PVP) buffer layerswere prepared from 2 wt. % solutions of PVP (M_(w)˜20,000) and poly(melamine-co-formaldehyde), as a cross-linking agent, in propyleneglycol monomethyl ether acetate (PGMEA), which were deposited by spincoating at 3000 rpm for 40 sec and subsequently cross-linked at 175° C.on a hot plate for 1 h in a N₂-filled glove box. Au (50 nm)bottom-contact source/drain electrodes were deposited by thermalevaporation through a shadow mask. A self-assembled monolayer ofpentafluorobenzenethiol (PFBT) was formed on the Au electrodes byimmersion in a 10 mmol PFBT solution in ethanol for 15 min in aN₂-filled dry box, rinsing with pure ethanol, and drying. TheTIPS-pentacene and PTAA blend solution was prepared as follows:TIPS-pentacene and PTAA were individually dissolved in1,2,3,4-Tetrahydronaphthalene anhydrous, 99%, (Sigma Aldrich) for aconcentration of 30 mg/mL and the two individual solutions were mixed toyield a weight ratio of 1:1. TIPS-pentacene and PTAA blend active layerswere deposited by spin coating at 500 rpm for 10 sec and at 2000 rpm for20 sec. Then, samples were dried at room temperature for 5 min andannealed at 40° C. for 16 h and at 100° C. for 15 min in a N₂-filled drybox. CYTOP (40 nm)/Al₂O₃ (50 nm) layers were used as top-gatedielectrics. CYTOP solution (CTL-809M) was purchased from Asahi Glasswith a concentration of 9 wt. %. To deposit the 40 nm-thick CYTOPlayers, the original solution diluted with their solvents (CT-solv. 180)to have solution:solvent ratios of 1:3.5. The 40 nm-thick CYTOP layerswere deposited by spin casting at 3000 rpm for 60 sec. The CYTOP (40 nm)films were annealed at 100° C. for 20 min. All spin coating andannealing processes were carried out in a N₂-filled dry box. Then, theAl₂O₃ dielectric films (50 nm) were deposited on top of the CYTOP layerusing a Savannah 100 ALD system from Cambridge Nanotech Inc. Films weregrown at 110° C. using alternating exposures of trimethyl aluminum[Al(CH₃)₃] and H₂O vapor at a deposition rate of approximately 0.1 nmper cycle. Finally, Al (150 nm) gate electrodes were deposited bythermal evaporation through a shadow mask. The resulting OFET isdepicted in FIG. 4B.

Example 2 Pentacene Channel Based OFET

The top gate pentacene OFETs were fabricated with a geometryincorporating a bottom source/drain electrodes. Au (80 nm) bottomcontact source/drain electrodes were deposited by electron-beam (e-beam)at room temperature on a glass substrate through a shadow mask. Apentacene active layer (50 nm) was then deposited by thermal evaporationat room temperature through a shadow mask. CYTOP (40 nm)/Al₂O₃ (50 nm)layers were used as a top gate dielectric. CYTOP (40 nm) layers werecoated by spin casting at 3000 rpm for 60 seconds. The CYTOP films wereannealed at 100° C. for 20 min. Al₂O₃ dielectric films were grown at110° C. using alternating exposures of trimethyl aluminum [Al(CH₃)₃] andH₂O vapor at a deposition rate of approximately 0.1 nm per cycle. Then,Al electrode was sequentially deposited by e-beam to form the gateelectrode.

Example 3 InGaZnO Channel Based Oxide FET

The top gate amorphous InGaZnO FET was fabricated with a geometryincorporating a bottom source/drain electrodes. First, a tri-layer of Ti(6 nm)/Au (50 nm)/Ti (6 nm) was deposited using electron-beam (e-beam)at room temperature on a glass substrate (Corning 1737) and patterned byphotolithography followed by a lift-off process. A 40 nm-thick a-IGZO(Ga₂O₃:In₂O₃:ZnO=1:1:2 mol %) active layer was then deposited by radiofrequency (RF) sputtering. After deposition of the a-IGZO layer, thedevice was annealed. To define the channel, the a-IGZO layer waspatterned by a wet-etching process using hydrochloric acid(HCl:H₂O=1:100) diluted in DI water. CYTOP (40 nm)/Al₂O₃ (50 nm) layerswere used as top gate dielectrics. Al₂O₃ dielectric films were grown at110° C. using alternating exposures of trimethyl aluminum [Al(CH₃)₃] andH₂O vapor. For 40 nm CYTOP layer, a 2 wt % solution was used, which wasdiluted with solvent. CYTOP (40 nm) layers were coated by spin castingat 3000 rpm for 60 seconds. The CYTOP films were annealed at 100° C. for20 min. Then, Ti (6 nm) and Au (120 nm) were sequentially deposited bye-beam and patterned by photolithography and lift-off process to formthe gate electrode.

Example 4 TIPS-Pentacene and PTAA OFET with CYTOP/SiN_(x) Bi-Layer

Example 4 is identical to example 1, with this difference that, insteadof depositing Al₂O₃ using an ALD process, an SiN_(X) material isdeposited by plasma-enhanced chemical vapor deposition (PECVD) at aprocess temperature of 110° C. Note that it is also possible to work ata higher temperature depending on the glass transition temperature ofthe fluoropolymer and semiconductor layer in the case of an amorphoussemiconductor layer.

Example 5 TIPS-Pentacene and PTAA OFET with Hyflon/Al₂O₃ Bi-Layer

Example 5 is identical to example 1, with this difference that, insteadof depositing CYTOP, a 40 nm layer of Hyflon AD 40X material isdeposited.

Example 6 TIPS-Pentacene and PTAA OFET with Teflon/Al₂O₃ Bi-Layer

Example 6 is identical to example 1, with this difference that, insteadof depositing CYTOP, a 40 nm layer of Teflon material is deposited.

Although the examples above relate to top gate FETs, the skilled personwill understand that bottom gate FETs can be fabricated in a more orless similar way.

Example 7 TIPS-Pentacene and Poly (Triarylamine) (PTAA) Blend ChannelBased OFET with CYTOP/Al₂O₃ Bi-Layer Using Plastic Substrate

OFETs with a bottom-contact and top-gate structure were fabricated on aflexible polyethersulfone (PES) substrate. Poly-4-vinylphenol (PVP)buffer layers were prepared from 2 wt. % solutions of PVP (M_(w)˜20,000)and poly (melamine-co-formaldehyde), as a cross-linking agent, inpropylene glycol monomethyl ether acetate (PGMEA), which were depositedby spin coating at 3000 rpm for 40 sec and subsequently cross-linked at175° C. on a hot plate for 1 h in a N₂-filled glove box. Au (50 nm)bottom-contact source/drain electrodes were deposited by thermalevaporation through a shadow mask. A self-assembled monolayer ofpentafluorobenzenethiol (PFBT) was formed on the Au electrodes byimmersion in a 10 mmol PFBT solution in ethanol for 15 min in aN₂-filled dry box, rinsing with pure ethanol, and drying. TheTIPS-pentacene and PTAA blend solution was prepared as follows:TIPS-pentacene and PTAA were individually dissolved in1,2,3,4-Tetrahydronaphthalene anhydrous, 99%, (Sigma Aldrich) for aconcentration of 30 mg/mL and the two individual solutions were mixed toyield a weight ratio of 1:1. TIPS-pentacene and PTAA blend active layerswere deposited by spin coating at 500 rpm for 10 sec and at 2000 rpm for20 sec. Then, samples were annealed at 100° C. for 15 min in a N₂-filleddry box. CYTOP (40 nm)/Al₂O₃ (50 nm) layers were used as top-gatedielectrics. CYTOP solution (CTL-809M) was purchased from Asahi Glasswith a concentration of 9 wt. %. To deposit the 40 nm-thick CYTOPlayers, the original solution diluted with their solvents (CT-solv. 180)to have solution:solvent ratios of 1:3.5. The 40 nm-thick CYTOP layerswere deposited by spin casting at 3000 rpm for 60 sec. The CYTOP (40 nm)films were annealed at 100° C. for 20 min. All spin coating andannealing processes were carried out in a N₂-filled dry box. Then, theAl₂O₃ dielectric films (50 nm) were deposited on top of the CYTOP layerusing a Savannah 100 ALD system from Cambridge Nanotech Inc. Films weregrown at 110° C. using alternating exposures of trimethyl aluminum[Al(CH₃)₃] and H₂O vapor at a deposition rate of approximately 0.1 nmper cycle. Finally, Al (150 nm) gate electrodes were deposited bythermal evaporation through a shadow mask. The resulting OFET isdepicted in FIG. 4C.

Example 8 TIPS-Pentacene and Poly (Triarylamine) (PTAA) Blend ChannelBased OFET with CYTOP/Al₂O₃ Bi-Layer (45 nm CYTOP; 50 nm Al₂O₃)

OFETs with a bottom-contact and top-gate structure were fabricated onglass substrates (Corning, Eagle 2000). Au (50 nm) bottom-contactsource/drain electrodes were deposited by thermal evaporation through ashadow mask. A self-assembled monolayer of pentafluorobenzenethiol(PFBT) was formed on the Au electrodes by immersion in a 10 mmol PFBTsolution in ethanol for 15 min in a N₂-filled dry box, rinsing with pureethanol, and drying. The TIPS-pentacene and PTAA blend solution wasprepared as follows: TIPS-pentacene and PTAA were individually dissolvedin 1,2,3,4-Tetrahydronaphthalene anhydrous, 99%, (Sigma Aldrich) for aconcentration of 30 mg/mL and the two individual solutions were mixed toyield a weight ratio of 1:1. TIPS-pentacene and PTAA blend active layerswere deposited by spin coating at 500 rpm for 10 sec and at 2000 rpm for20 sec. Then, samples were annealed at 100° C. for 15 min in a N₂-filleddry box. CYTOP (45 nm)/Al₂O₃ (50 nm) layers were used as top-gatedielectrics. CYTOP solution (CTL-809M) was purchased from Asahi Glasswith a concentration of 9 wt. %. To deposit the 45 nm-thick CYTOPlayers, the original solution diluted with their solvents (CT-solv. 180)to have solution:solvent ratios of 1:3.5. The 45 nm-thick CYTOP layerswere deposited by spin casting at 3000 rpm for 60 sec. The CYTOP (45 nm)films were annealed at 100° C. for 20 min. All spin coating andannealing processes were carried out in a N₂-filled dry box. Then, theAl₂O₃ dielectric films (50 nm) were deposited on top of the CYTOP layerusing a Savannah 100 ALD system from Cambridge Nanotech Inc. Films weregrown at 110° C. using alternating exposures of trimethyl aluminum[Al(CH₃)₃] and H₂O vapor at a deposition rate of approximately 0.1 nmper cycle. Finally, Al (150 nm) gate electrodes were deposited bythermal evaporation through a shadow mask. The resulting OFET isdepicted in FIG. 4D.

Example 9 diF-TESADT and Poly (Triarylamine) (PTAA) Blend Channel BasedOFET with CYTOP/Al₂O₃ Bi-Layer (45 nm CYTOP; 50 nm Al₂O₃)

Example 9 is identical to example 8, except2,8-difluoro-5,11-bis(triethylsilylethynyl) anthradithiophene(diF-TESADT) was used rather than TIPS-pentacene. The structure ofdiF-TESADT is shown below:

The resulting OFET is depicted in FIG. 4E.

Example 10 TIPS-Pentacene and Poly (Triarylamine) (PTAA) Blend ChannelBased OFET with CYTOP/Al₂O₃/CYTOP Tri-Layer (20 nm CYTOP; 50 nm Al₂O₃^(.) 20 nm CYTOP)

OFETs with a bottom-contact and top-gate structure were fabricated onglass substrates (Corning, Eagle 2000). Au (50 nm) bottom-contactsource/drain electrodes were deposited by thermal evaporation through ashadow mask. A self-assembled monolayer of pentafluorobenzenethiol(PFBT) was formed on the Au electrodes by immersion in a 10 mmol PFBTsolution in ethanol for 15 min in a N₂-filled dry box, rinsing with pureethanol, and drying. The TIPS-pentacene and PTAA blend solution wasprepared as follows: TIPS-pentacene and PTAA were individually dissolvedin 1,2,3,4-Tetrahydronaphthalene anhydrous, 99%, (Sigma Aldrich) for aconcentration of 30 mg/mL and the two individual solutions were mixed toyield a weight ratio of 1:1. TIPS-pentacene and PTAA blend active layerswere deposited by spin coating at 500 rpm for 10 sec and at 2000 rpm for20 sec. Then, samples were annealed at 100° C. for 15 min in a N₂-filleddry box. CYTOP (45 nm)/Al₂O₃ (50 nm) layers were used as top-gatedielectrics. CYTOP solution (CTL-809M) was purchased from Asahi Glasswith a concentration of 9 wt. %. To deposit the 20 nm-thick CYTOPlayers, the original solution diluted with their solvents (CT-solv. 180)to have solution:solvent ratios of 1:7. The 20 nm-thick CYTOP firstlayers were deposited by spin casting at 3000 rpm for 60 sec. The CYTOP(20 nm) films were annealed at 100° C. for 20 min. Then, the Al₂O₃dielectric films (50 nm) were deposited on top of the CYTOP layer usinga Savannah 100 ALD system from Cambridge Nanotech Inc. Films were grownat 110° C. using alternating exposures of trimethyl aluminum [Al(CH₃)₃]and H₂O vapor at a deposition rate of approximately 0.1 nm per cycle.The 20 nm-thick CYTOP third layers were deposited on the top of Al₂O₃second layers. The CYTOP (20 nm) films were annealed at 100° C. for 20min. All spin coating and annealing processes were carried out in aN₂-filled dry box. Finally, Al (150 nm) gate electrodes were depositedby thermal evaporation through a shadow mask. The resulting OFET isdepicted in FIG. 4F.

Example 11 Pentacene and InGaZnO Based FETs and Inverters

Organic-inorganic hybrid complementary inverters were fabricated with atop gate and bottom-contact source and drain electrode geometry. First,Ti/Au (6 nm/50 nm) electrodes were deposited using electron-beam(e-beam) at room temperature on a glass substrate through a shadow maskto define the source and drain electrodes. Non-overlapping pentacene(hole transport) and a-IGZO (electron transport) channels horizontallydistributed with different aspect ratios were fabricated on top of thesource/drain electrodes. A 30 nm-thick a-IGZO (Ga₂O₃:In₂O₃:ZnO=1:1:1 mol%) active layer was deposited at room temperature by rf-sputteringthrough a shadow mask using a power of 125 W at a working pressure of 3mTorr in an O₂/Ar (2%/98%) atmosphere. These structures were annealed at300° C. for 30 minutes in air. Then, a 50 nm-thick layer of pentacenewas deposited through a shadow mask using thermal evaporation with asubstrate temperature of 25° C. and an initial pressure of 2×10⁻⁸ Torr.Prior to thermal evaporation, pentacene was purified using gradient zonesublimation. CYTOP (40 nm)/Al₂O₃ (50 nm) layers were used as top-gatedielectrics. CYTOP solution (CTL-809M) was purchased from Asahi Glasswith a concentration of 9 wt. %. To deposit the 45 nm-thick CYTOPlayers, the original solution diluted with their solvents (CT-solv. 180)to have solution:solvent ratios of 1:3.5. The 45 nm-thick CYTOP layerswere deposited by spin casting at 3000 rpm for 60 sec. The CYTOP (45 nm)films were annealed at 100° C. for 20 min. All spin coating andannealing processes were carried out in a N₂-filled dry box. Then, theAl₂O₃ dielectric films (50 nm) were deposited on top of the CYTOP layerusing a Savannah 100 ALD system from Cambridge Nanotech Inc. Films weregrown at 110° C. using alternating exposures of trimethyl aluminum[Al(CH₃)₃] and H₂O vapor at a deposition rate of approximately 0.1 nmper cycle. Finally, Al (50 nm) gate electrodes were deposited by thermalevaporation through a shadow mask. The resulting inverter is depicted inFIG. 4G.

Example 12 Polyera ActivInk N2200 Based OFET with CYTOP/Al₂O₃ Bi-Layer(45 nm CYTOP; 50 nm Al₂O₃) and Evaporated Au Source/Drain Electrodes

OFETs with a bottom-contact and top-gate structure were fabricated onglass substrates (Corning, Eagle 2000). Au (50 nm) bottom-contactsource/drain electrodes were deposited by thermal evaporation through ashadow mask Inkjet printing semiconductor formulations are based on NDIpolymerpoly{[N,N9-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,59-(2,29-bithiophene)},(P(NDI2OD-T2), Polyera ActivInk N2200. P(NDI2OD-T2) ink was prepared asfollows: NDI polymer was dissolved in mixture of1,2,3,4-Tetrahydronaphthalene anhydrous, 99% (Sigma Aldrich) andmesitylene, 99% (Sigma Aldrich) with a ratio of 1:1 in volume in orderto reach 0.5% concentration in active material. Formulation was stirredover night in ambient. The structure of Polyera ActivInk N2200 is shownbelow:

A Dimatix DMP 2831 inkjet printing system was used to patternsemiconductor layers. Around 150 nm thick layer of active material wasprinting in air at room temperature. CYTOP (45 nm)/Al₂O₃ (50 nm) layerswere used as top-gate dielectrics. CYTOP solution (CTL-809M) waspurchased from Asahi Glass with a concentration of 9 wt. %. To depositthe 45 nm-thick CYTOP layers, the original solution diluted with theirsolvents (CT-solv. 180) to have solution:solvent ratios of 1:3.5. The 45nm-thick CYTOP layers were deposited by spin casting at 3000 rpm for 60sec. The CYTOP (45 nm) films were annealed at 100° C. for 20 min. Allspin coating and annealing processes were carried out in a N₂-filled drybox. Then, the Al₂O₃ dielectric films (50 nm) were deposited on top ofthe CYTOP layer using a Savannah 100 ALD system from Cambridge NanotechInc. Films were grown at 110° C. using alternating exposures oftrimethyl aluminum [Al(CH₃)₃] and H₂O vapor at a deposition rate ofapproximately 0.1 nm per cycle. Finally, Al (100 nm) gate electrodeswere deposited by thermal evaporation through a shadow mask. Theresulting OEFT is depicted in FIG. 4H.

Example 13 Polyera ActivInk N2200 Based OFET with CYTOP/Al₂O₃ Bi-Layer(45 nm CYTOP; 50 nm Al₂O₃) and Evaporated Ag Source/Drain Electrodes

Example 13 is identical to example 12, except that Ag was used insteadof Au in the bottom-contact source/drain electrodes.

Example 14 Polyera ActivInk N2200 Based OFET with CYTOP/Al₂O₃ Bi-Layer(45 nm CYTOP; 50 nm Al₂O₃) and Printed Ag Source/Drain Electrodes

Example 14 is identical to example 14, except that the Ag bottom-contactsource/drain electrodes were patterned by a Dimatix DMP 2831 inkjetprinter.

Example 15 LEH-III-002a Based OFET with CYTOP/Al₂O₃ Bi-Layer (45 nmCYTOP; 50 nm Al₂O₃)

OFETs with bottom contact and top gate structure were fabricated onglass substrates (Corning, Eagle 2000). Au (50 nm), Al (50 nm), and Ag(50 nm) bottom contact source/drain electrodes were deposited by thermalevaporation through a shadow mask. Thin films of organic semiconductorsof LEH-III-002a (LEH-III085g, LEH-119a) were deposited by spin coatingwith a 30 mg/ml solution prepared from dichlorobenzene at 500 rpm for 10second followed by 2000 rpm for 20 seconds. LEH-III-002a (LEH-III-085g,LEH-III-119a) is shown in the formula below:

The blend for polymer matrix with poly(α-methyl styrene) (PαMS) (M_(w)100,000) was prepared from mixing separate 30 mg/ml solutions ofLEH-III-119a (LEH-III-085g) and PαMS. Poly(α-methyl styrene) (PαMS)(M_(w) 100,000) is shown in the formula below:

The blend films were deposited by spin coating at 500 rpm for 10 secondfollowed by at 2000 rpm for 20 seconds. The sole and blend films wereannealed at 100° C. for 15 min. CYTOP (45 nm)/Al₂O₃ (50 nm) layers wereused as top-gate dielectrics. CYTOP solution (CTL-809M) was purchasedfrom Asahi Glass with a concentration of 9 wt. %. To deposit the 45nm-thick CYTOP layers, the original solution diluted with their solvents(CT-solv. 180) to have solution:solvent ratios of 1:3.5. The 45 nm-thickCYTOP layers were deposited by spin casting at 3000 rpm for 60 sec. TheCYTOP (45 nm) films were annealed at 100° C. for 20 min. All spincoating and annealing processes were carried out in a N₂-filled dry box.Then, the Al₂O₃ dielectric films (50 nm) were deposited on top of theCYTOP layer using a Savannah 100 ALD system from Cambridge Nanotech Inc.Films were grown at 110° C. using alternating exposures of trimethylaluminum [Al(CH₃)₃] and H₂O vapor at a deposition rate of approximately0.1 nm per cycle. Finally, Al (150 nm) gate electrodes were deposited bythermal evaporation through a shadow mask.

Example 16 DRR-IV-209n Based OFET with CYTOP/Al₂O₃ Bi-Layer (45 nmCYTOP; 50 nm Al₂O₃)

OFETs with bottom contact and top gate structure were fabricated onglass substrates (Corning, Eagle 2000). Au (50 nm) bottom contactsource/drain electrodes were deposited by thermal evaporation through ashadow mask. Organic semiconductor layers of DRR-IV-209n were formed onthe substrates by spin coating with a solution prepared from 1,4-dioxane(20 mg/mL) and dichlorobenzene (20 mg/mL) at 500 rpm for 10 sec and at2,000 rpm for 20 sec. DRR-IV-209n is shown in the formula below:

Then, samples were annealed at 100° C. (1,4-dioxane sample) and 120° C.(dichlorobenzene sample) for 10 min in a N₂-filled dry box. CYTOP (45nm)/Al₂O₃ (50 nm) layers were used as top-gate dielectrics. CYTOPsolution (CTL-809M) was purchased from Asahi Glass with a concentrationof 9 wt. %. To deposit the 45 nm-thick CYTOP layers, the originalsolution diluted with their solvents (CT-solv. 180) to havesolution:solvent ratios of 1:3.5. The 45 nm-thick CYTOP layers weredeposited by spin casting at 3000 rpm for 60 sec. The CYTOP (45 nm)films were annealed at 100° C. for 20 min. All spin coating andannealing processes were carried out in a N₂-filled dry box. Then, theAl₂O₃ dielectric films (50 nm) were deposited on top of the CYTOP layerusing a Savannah 100 ALD system from Cambridge Nanotech Inc. Films weregrown at 110° C. using alternating exposures of trimethyl aluminum[Al(CH₃)₃] and H₂O vapor at a deposition rate of approximately 0.1 nmper cycle. Finally, Al (150 nm) gate electrodes were deposited bythermal evaporation through a shadow mask.

Comparative Study of OFETs with Different CYTOP Layer/Al₂O₃ LayerThicknesses

For illustrating the advantages of the embodiments of the invention, thefollowing study has been made of the OFET structure of FIG. 4A. FiveOFETs with different CYTOP layer/Al₂O₃ layer thicknesses have beencompared:

CYTOP (25 nm)/Al₂O₃ (50 nm);

CYTOP (40 nm)/Al₂O₃ (50 nm);

CYTOP (530 nm)/Al₂O₃ (50 nm);

Al₂O₃ (100 nm) layer as gate dielectric;

CYTOP (780 nm) layer as gate dielectric.

In all studied OFETs the substrate 301 is a Poly-4-vinylphenol(PVP)-coated glass substrate and the semiconductor material 302 is aTIPS-pentacene and PTAA blend, spin-coated on the substrate. Afterdeposition, the blended films of TIPS-pentacene and PTAA were annealedto induce vertical-phase segregation. Gold (50 nm) and aluminum (150 nm)were used as bottom-contact source/drain electrodes and top-gateelectrode, respectively. Prior to the deposition of the semiconductorlayer, the surface of the gold electrodes was treated with aself-assembled monolayer of pentafluorobenzenethiol (PFBT) to improvecontact between the metal and organic interface.

FIG. 5 compares the ratio of the drain-source current I_(DS) withrespect to the initial drain current I_(DS0) in function of time undercontinuous bias stress in the OFET of FIG. 4A for three different CYTOPlayer thicknesses (V_(G)=V_(D)=−6V, −8V, −25V for t_(CYTOP)=25, 40, 530nm, respectively). Those measurements show that by choosing anappropriate CYTOP layer thickness, the evolution of the drain current infunction of time under continuous bias stress can be influenced. In thisexample the CYTOP layer thickness of 40 nm gives the best results. Notethat the optimal value for this CYTOP layer thickness will be influencedby the thickness of the Al₂O₃ layer and the dielectric constants. Thiscan be better understood by considering the following formula and FIGS.6A and 6B.

Electric field within each layer:

$\mspace{20mu} {E_{i} = {\frac{\text{?}}{k_{j}t_{i}\text{?}k_{i}t_{j}}V_{G}}}$?indicates text missing or illegible when filed

Effective voltage within each layer:

$\mspace{20mu} {V_{i} = {\frac{\text{?}}{k_{j} + {k_{i}\text{?}\text{?}\text{?}}}V_{G}}}$?indicates text missing or illegible when filed

wherein E_(i) and V_(i) refers to the electric field and effectivevoltage, respectively, in a layer i having a thickness t, and dielectricconstant k_(i), wherein the gate dielectric consists of layer i and alayer j having a thickness t_(j) and dielectric constant k_(j).

These equations are illustrated in FIG. 6A. As shown in FIG. 6B theeffects on the change in voltage over the CYTOP layer in function of achange in dielectric constant of the Al₂O₃ layer is larger for smallervalues of the CYTOP layer thickness. Such a slope is necessary in orderto obtain the above described compensation effect. For thick CYTOPlayers, e.g. the 500 nm curve in FIG. 6B, the curve is almost flatindicating that compensation will not be reached (wherein it is assumedthat the other dielectric constants remain the same).

FIGS. 7A and 7B show the capacitance density-electric field (C-E) andcurrent density-electric field (J-E) characteristics of Al₂O₃ (100 nm),CYTOP (780 nm), and CYTOP (40 nm)/Al₂O₃ (50 nm) films, respectively. Thedielectric properties of all films were characterized using aparallel-plate capacitor geometry of gold (100 nm)/dielectric/indiumthin oxide (ITO) coated glass with various areas ranging from 3.1×10-4cm² to 2.4×10-1 cm². The measured capacitance densities (C_(in)) of theAl₂O₃ and CYTOP films at a frequency of 1 kHz were 78.6 and 2.3 nF/cm²,respectively. The extracted dielectric constant (k) values are 8.9 forAl₂O₃ and 2.0 for CYTOP. The CYTOP/Al₂O₃ bi-layer exhibited a C_(m) of34.8 nF/cm² at a frequency of 1 kHz, which is close to the theoreticalvalue (34.6 nF/cm²) estimated from a series-connected capacitor of CYTOPand Al₂O₃. As shown in FIG. 7B, the leakage current densities of theAl₂O₃ and CYTOP/Al₂O₃ films remained below 3×10⁻⁷ A/cm² at appliedfields with a magnitude up to 3 MV/cm. In contrast, the leakage currentof a 780-nm-thick CYTOP film reached a value of 2×10⁻⁷ A/cm² at anapplied field of 1.2 MV/cm.

FIGS. 8A-8B show the transfer and output characteristics, measured frompristine devices under a nitrogen atmosphere, of OFETs (W/L=2550 μm/180μm) using a CYTOP (40 nm)/Al₂O₃ (50 nm) gate dielectric. The OFETsshowed no hysteresis and achieved a maximum value of μ=0.6 cm²/Vs at alow voltage of 8 V due to the relatively high C_(in), of the bi-layergate dielectric. Average values of the mobility μ=0.46±0.08 cm²/Vs, thethreshold voltage V_(th)=−2.4±0.1 V, I_(on)/I_(off)=10⁵, thesub-threshold slope SS=0.20±0.06 V/decade and a maximum interfacial trapdensity of 5×10¹¹ cm⁻² were measured in these bi-layer devices. Comparedwith OFETs using the CYTOP single layer, OFETs using the bi-layer showsimilar values of μ but smaller values of V_(th) and SS and highervalues of I_(on)/I_(off) at low operating voltages due to the highC_(in).

FIG. 9A shows a table that summarizes the different conditions ofenvironmental exposure and electrical stress to which each set of OFETswas subjected to study their long-term environmental and operationalstabilities. To study their environmental stability, all OFETs wereexposed to a normal ambient condition at a relative humidity between 30and 50%. Variations of μ and V_(th) were monitored at discreteintervals. At each interval, each substrate was transferred back into aN₂-filled glove box for electrical measurements and operationalstability tests.

FIG. 9B shows that, in the different types of OFETs, no significantchange in μ was observed after up to 31 days of exposure to air. As willbe shown, the good air stability of TIPS-pentacene also contributes tothe environmental stability of these OFETs. In OFETs with the Al₂O₃ gatedielectric, a gradual increase of the average value of μ from 5.5(±2.0)×10⁻³ cm²/V up to 1.1 (±0.4)×10⁻² cm²/Vs was observed. In theother OFETs, after an initial increase within the first eleven days, μremained unchanged with average values of 0.60±0.20 cm²/Vs for OFETswith the CYTOP gate dielectric and 0.52±0.09 cm²/Vs for OFETs with theCYTOP/Al₂O₃ gate dielectric. On the other hand, the variations of V_(th)for the devices with different gate dielectrics are shown in FIG. 9C. InOFETs with the Al₂O₃ gate dielectric, the average value of V_(th),measured from sweeps of V_(GS) from off-to-on regime, varied from−2.4±0.3 V to −2.8±0.3 V after 31 days in air. Despite this seeminglysmall change, strong hysteresis and large device-to-device variation ofthe magnitude and sign of V_(th) were observed in these devices. Incontrast, in hysteresis-free OFETs with the CYTOP gate dielectric, alarge positive shift in V_(th) from −24.3±0.8 V to −4.0±0.7 V wasobserved after 11 days in air. After this initial variation, no seriousshift in V_(th) was observed, reaching a value of −3.7±0.3 V after 31days in air. Similar changes, albeit of a smaller magnitude, wereobserved in hysteresis-free OFETs with the CYTOP/Al₂O₃ bi-layer. After31 days in air, only a minor shift in V_(th) from −2.5±0.1 V to −1.4±0.1V was measured. As in devices with the CYTOP gate dielectric, most ofthese changes happened within the first 11 days.

FIG. 9D shows the variations of the mobility and the threshold voltageV_(th) For an OFET with a CYTOP (40 nm)/Al₂O₃ (50 nm) film.

To study the encapsulation properties of our top-gate dielectrics, Cathin-film optical transmission tests were carried out. It was found thatCa films protected with a CYTOP single layer rapidly oxidized within anhour of being exposed to air, while Ca films protected with either aCYTOP/Al₂O₃ bi-layer or an Al₂O₃ single layer started degradation onlyafter being exposed to air for more than a day. From these experiments,it is expected that CYTOP is a protective barrier for H₂O diffusion dueto its hydrophobic nature, so O₂ diffusion should be responsible for thedegradation of the Ca layers. OFETs using the bi-layer gate dielectricshowed superior environmental stability compared with those usingsingle-layer gate dielectrics.

The encapsulation properties of the dielectrics used in the top-gateOFETs were further tested, after 31 days in air, by exposing them to anO₂ plasma for 5 min at a power of 750 W, a condition which is moresevere than air exposure due to the high reactivity of the O₂ plasma,known to remove organic residues and other contaminants from surfaces.FIGS. 9B and 9C show that, after O₂ plasma treatment, no serious changesin μ or V_(th) were observed for all three types of OFETs. A significantchange observed in the electrical characteristics of the different OFETswas a severe increase of I_(off) in the OFETs with a single CYTOP layer.On the other hand, Al₂O₃ acts as a protective layer to the energetic O₂plasma, so no significant changes in the I_(on)/I_(off) ratios wereobserved in the devices with Al₂O₃ and CYTOP/Al₂O₃ gate dielectrics. Asdescribed in FIG. 9A, after O₂ plasma treatment, the electricalproperties of the OFETs with a CYTOP/Al₂O₃ bi-layer were tested after anaccumulated air exposure up to 210 days (7 months). FIGS. 9B and 9C showthat the average values of μ and V_(th) remain practically unchanged.

In addition to the environmental stability, the operational stability isof critical importance for circuit design and overall device lifetime.The mechanisms of degradation under continuous operation are related tocharge trapping and de-trapping events at all of the critical interfacesin an OFET and in the bulk of the semiconductor and gate dielectric. Thedegradation of the performance of an OFET during operation is reflectedin changes of μ and V_(th). Because the trap dynamics depend on thedensity of carriers flowing through the channel, a more severedegradation is expected when transistors are operated at higher powers.Other mechanisms like the diffusion of mobile impurities or thepolarization of the gate dielectric could also contribute to thedegradation of the performance. For these reasons, the operationalstability of all OFETs was evaluated in two ways: 1) by multiplecontinuous scans of the transfer characteristic and 2) by applying aconstant direct current (DC) bias stress, a more severe condition due tothe higher current densities flowing through the channel.

FIGS. 10A and 10B show a sampling of the transfer curves measured in aCYTOP (40 nm)/Al₂O₃ (50 nm) OFETs during multiple continuous scans fromthe “off” to the “on” region, before (FIG. 10A) and after (FIG. 10B) airexposure for 31 days. Negligible changes in the transfercharacteristics, during the first 1000 scans, were observed in OFETswith a CYTOP/Al₂O₃ gate dielectric, as shown in the inset of FIG. 10A,before the OFETs were exposed to air. To further test the operationalstability of these devices before exposing them to air, both weresubjected to an additional 20,000 scans. FIG. 10A shows that even undersuch conditions, negligible changes were observed in the transfercharacteristics of both kinds of OFETs. Even after being exposed to airfor 31 days, the operational stability under multiple continuous scanswas preserved, as shown in FIG. 10B. This remarkable stability is aconsequence of the excellent electrical properties of theCYTOP/TIPS-pentacene interface.

As shown in FIG. 9A, before exposing the OFETs to air and after 1000scans, devices 1 of the different types of OFETs were subjected to 3600s (1 h) of DC bias stress. FIG. 11A shows the temporal evolution of theI_(DS) measured in all OFETs normalized to the initial value. In theOFET with the Al₂O₃ gate dielectric, a drop in the normalized I_(DS) wasmeasured, reaching a final value of 0.77 after 1 h. During the sameinterval, the current measured in a CYTOP device dropped to 0.9.However, the evolution of the CYTOP/Al₂O₃ bi-layer is different in thatthe current slightly increases, reaching a value of 1.04 after 1 h. FIG.11B shows the evolution of the normalized I_(DS) measured in all OFETsfor 1 h bias stress after 31 days of exposure to air (devices 2). InOFETs with the bi-layer gate dielectric, the mechanism driving theslight increase of I_(DS) is significantly different from the oneobserved in the other OFETs. Furthermore, the operational stability ofOFETs with the bi-layer gate dielectric was tested after O₂ plasmatreatment by monitoring the current change over 24 h of electrical biasstress. FIG. 11C shows that changes in the normalized I_(DS) remainbelow 4% its original value. As shown in FIG. 11D, this remarkablestability results in negligible changes of the transfer and outputcharacteristics before and after DC bias stress. It should be notedthat, as found before, I_(DS) shows a slight increase during the initialstages of the DC bias stress but slowly decreased after prolongedstress. FIG. 11E shows the temporal evolution of the I_(DS) over 24 h ofelectrical bias stress measured in an OFET with a CYTOP (40 nm)/Al₂O₃(50 nm) film for: a pristine OFET (Dev. 1), after 31 days of exposed inair (Dev. 2), after O₂ plasma treatment (Dev. 3), after air exposure 90days (Dev. 4), after air exposure for 150 days (Dev. 5), after airexposed for 210 days (Dev. 6), and after air exposure for 365 days (Dev.7). As can be seen, the variation of I_(DS) under DC bias was less than±10%.

The remarkable stability of the OFETs with the bi-layers underelectrical bias arises from compensating effects: 1) a decrease inI_(DS) caused by intrinsic deep traps at the CYTOP/TIPS-pentaceneinterface and 2) an increase in I_(DS) caused by dipoles that can beoriented at the CYTOP/Al₂O₃ interface and/or by charge injection andtrapping at the gate dielectric.

Systematic Stability Study on OFETs with CYTOP/Al₂O₃ Bi-Layer Dielectric

For illustrating the advantages of the embodiments of the invention, thefollowing study has been made on OFETs with CYTOP/Al₂O₃ bi-layerdielectric. The effects of O₂ and H₂O exposure on p-channel OFETs werestudied.

The generalized effects of O₂ and H₂O exposure on the transfercharacteristics of such OFETs is depicted in FIGS. 16A and 16B. FIG. 16Ashows that O₂ has both doping and oxidation effects, the doping effecttending to shift the transfer characteristic curve to the right, and theoxidation effect tending to shift the transfer characteristic curve tothe left. FIG. 16B shows that H₂O increases dielectric polarization,which tends to shift the transfer characteristic curve to the right, butalso has the effect of trap creation, which tends to shift the transfercharacteristic curve to the left.

The generalized effects of O₂ and H₂O exposure on the temporal evolutionof the I_(DS) during DC bias stress are shown in FIG. 16C. FIG. 16Cshows that O₂ exposure has little effect on I_(DS) during DC biasstress. H₂O exposure, however, causes a decrease in I_(DS) over timeduring DC bias stress.

To test the extent of these effects, three different OFETs were tested.The first was a TIPS-pentacene and PTAA blend channel based OFET with aCYTOP/Al₂O₃ bi-layer (45 nm CYTOP; 50 nm Al₂O₃), as shown in FIG. 4D.The second was a diF-TESADT and PTAA blend channel based OFET with aCYTOP/Al₂O₃ bi-layer (45 nm CYTOP; 50 nm Al₂O₃), as shown in FIG. 4E.The third was a TIPS-pentacene and PTAA blend channel based OFET with aCYTOP/Al₂O₃/CYTOP tri-layer (20 nm CYTOP; 50 nm Al₂O₃; 20 nm CYTOP), asshown in FIG. 4F. The OFETs were subject to the exposure sequence shownin FIG. 17.

FIGS. 18A-18C show the capacitance C_(in)(nF/cm²), mobility μ(cm²/Vs),and threshold voltage V_(th)(V) for each stage of the exposure sequence.These results indicate that the effects of O₂ and H₂O are reversible forCYTOP/Al₂O₃ bi-layer and CYTOP/Al₂O₃/CYTOP tri-layer OFETs.

FIGS. 19A and 19B show the variation in capacitance for frequenciesranging from 20 Hz to 1 million Hz, for the CYTOP/Al₂O₃ bi-layer OFET(45 nm CYTOP; 50 nm Al₂O₃) (FIG. 19A) and the CYTOP/Al₂O₃/CYTOPtri-layer OFET (20 nm CYTOP; 50 nm Al₂O₃; 20 nm CYTOP) (FIG. 19B), ateach stage of the exposure sequence.

FIGS. 20A and 20B show the transfer characteristics and temporalevolution of the I_(DS) during DC bias for the TIPS-pentacene and PTAAblend channel based OFET with a CYTOP/Al₂O₃ bi-layer (45 nm CYTOP; 50 nmAl₂O₃). The data obtained during testing of the OFET is summarized inthe table below.

FIGS. 21A and 21B show the transfer characteristics and temporalevolution

Average 9 devices Cin (nF/cm²) W/L μ (cm² /Vs) V_(th) (V) Pristine 35.2± 0.3 2550 μm/180 μm 0.57 ± 0.11 −3.4 ± 0.2 Dry O2 35.2 ± 0.3 2550μm/180 μm 0.69 ± 0.14 −2.7 ± 0.3 Vacuum 35.0 ± 0.3 2550 μm/180 μm 0.61 ±0.12 −3.4 ± 0.2 Humid air 37.5 ± 0.3 2550 μm/180 μm 0.61 ± 0.12 −2.6 ±0.2 Vacuum 34.4 ± 0.1 2550 μm/180 μm 0.64 ± 0.14 −3.4 ± 0.3 H2O (water)35.7 ± 0.3 2550 μm/180 μm 0.65 ± 0.15 −2.4 ± 0.2 Vacuum 34.5 ± 0.3 2550μm/180 μm 0.66 ± 0.14 −3.3 ± 0.3of the I_(DS) during DC bias for the diF-TESADT and PTAA blend channelbased OFET with a CYTOP/Al₂O₃ bi-layer (45 nm CYTOP; 50 nm Al₂O₃). Thedata obtained during testing of the OFET is summarized in the tablebelow.

Average 7 devices Cin (nF/cm²) W/L μ (cm²/Vs) V_(th) (V) Pristine 35.2 ±0.3 2550 μm/180 μm 1.21 ± 0.51 −3.1 ± 0.2 Dry O2 35.2 ± 0.3 2550 μm/180μm 1.25 ± 0.51 −2.5 ± 0.2 Vacuum 35.0 ± 0.3 2550 μm/180 μm 1.21 ± 0.51−3.0 ± 0.1 Humid air 37.5 ± 0.3 2550 μm/180 μm 1.14 ± 0.50 −2.5 ± 0.3Vacuum 34.4 ± 0.1 2550 μm/180 μm 1.19 ± 0.51 −3.0 ± 0.2 H2O (water) 35.7± 0.3 2550 μm/180 μm 1.19 ± 0.50 −2.4 ± 0.3 Vacuum 34.5 ± 0.3 2550μm/180 μm 1.18 ± 0.50 −2.9 ± 0.3

FIGS. 22A and 22B show the transfer characteristics and temporalevolution of the I_(DS) during DC bias for the TIPS-pentacene and PTAAblend channel based OFET with a CYTOP/Al₂O₃/CYTOP tri-layer (20 nmCYTOP; 50 nm Al2O3; 20 nm CYTOP). The data obtained during testing ofthe OFET is summarized in the table below.

Average 7 devices Cin (nF/cm²) W/L μ (cm² /Vs) V_(th) (V) Pristine 35.2± 0.3 2550 μm/180 μm 1.21 ± 0.51 −3.1 ± 0.2 Dry O2 35.2 ± 0.3 2550μm/180 μm 1.25 ± 0.51 −2.5 ± 0.2 Vacuum 35.0 ± 0.3 2550 μm/180 μm 1.21 ±0.51 −3.0 ± 0.1 Humid air 37.5 ± 0.3 2550 μm/180 μm 1.14 ± 0.50 −2.5 ±0.3 Vacuum 34.4 ± 0.1 2550 μm/180 μm 1.19 ± 0.51 −3.0 ± 0.2 H2O (water)35.7 ± 0.3 2550 μm/180 μm 1.19 ± 0.50 −2.4 ± 0.3 Vacuum 34.5 ± 0.3 2550μm/180 μm 1.18 ± 0.50 −2.9 ± 0.3

Comparative Study on Various Fluoropolymer (CYTOP, Hyflon, andTeflon)/Inorganic (Al₂O₃ and SiN_(x)) Bi-Layers

For illustrating the advantages of the embodiments of the invention, thefollowing study has been made of capacitors and OFETs havingfluoropolymer bi-layers. Eight capacitors and eight OFETs with differentfluoropolymer bi-layers have been compared.

CYTOP (45 nm)/Al₂O₃ (50 nm);

Hyflon (45 nm)/Al₂O₃ (50 nm);

Teflon (45 nm)/Al₂O₃ (50 nm);

CYTOP (20 nm)/Al₂O₃ (50 nm)/CYTOP (20 nm);

CYTOP (45 nm)/S_(i)N_(x) (50 nm);

Hyflon (45 nm)/S_(i)N_(x) (50 nm);

Teflon (45 nm)/S_(i)N_(x) (50 nm);

CYTOP (20 nm)/S_(i)N_(x) (50 nm)/CYTOP (20 nm).

To prepare the capacitors, Au (50 nm) bottom electrodes were depositedon glass substrates (Corning 1737) by thermal evaporation through ashadow mask. Various fluoropolymer (CYTOP, Hyflon, and Teflon)/inorganic(Al₂O₃ and SiN_(x)) bi-layers and CYTOP/inorganic (Al₂O₃ andSiN_(x))/CYTOP triple layers were used as dielectrics. CYTOP solution(CTL-809M) was purchased from Asahi Glass with a concentration of 9 wt.%. Hyflon solution (Hyflon® AD 40X) was received from Solvay, of whichconcentration is ˜6.6 wt %. Teflon solution (601S2-100-6) was purchasedfrom DuPont with a concentration of 6 wt. %. To deposit the 45-nm-thickfluoropolymer layers, the original solutions were diluted with theirsolvents (CT-solv. 180 for CYTOP, LS165 for Hyflon, and FC-40 forTeflon) to have solution:solvent ratios of 1:3.5 for CYTOP, 1:2 forHyflon, and 1:3 for Teflon. For 20 nm CYTOP layers, the solution:solventratio is 1:7. Fluoropolymer layers were deposited by spin coating at3000 (for CYTOP) and at 4000 rpm (for Hyflon and Teflon) for 60 sec.After deposition, fluoropolymer layers were annealed at 100° C. for 20min. Then, the Al₂O₃ dielectric films (50 nm) were deposited on top ofthe fluoropolymer layer using a Savannah 100 ALD system from CambridgeNanotech Inc. Films were grown at 110° C. using alternating exposures oftrimethyl aluminum [Al(CH₃)₃] and H₂O vapor at a deposition rate ofapproximately 0.1 nm per cycle. SiN_(x) films (50 nm) were deposited onfluoropolymer layers by plasma enhanced chemical vapor deposition(PECVD) at 110° C. For triple layer dielectrics, CYTOP films (20 nm)deposited on Al₂O₃ and SiN_(x) films and annealed at 100° C. for 20 min.Finally, Al (150 nm) top electrodes were deposited by thermalevaporation through a shadow mask.

FIGS. 23A-23D show the capacitance and current density-electric field(J-E) characteristics of the tested capacitors. A summary of thedielectric properties of the tested capacitors is contained in the Tablebelow.

C_(in) (nF/cm2) at 1 KHz Breakdown field Measured Cin (nF/cm²) (MV/cm)Dielectric type value Calculated value @ J = 10⁻⁶ A/cm² CYTOP (45nm)/Al₂O₃ (50 nm) 35.2 ± 0.3 34.6 Over 3.3 MV/cm CYTOP (20 nm)/Al₂O₃ (5034.6 ± 0.1 Over 3.3 MV/cm nm)/CYTOP (20 nm) Hyflon (45 nm)/Al₂O₃ (50 nm)39.1 ± 0.1 3 MV/cm Teflon (45 nm)/Al₂O₃ (50 nm) 34.7 ± 0.3 Over 3.3MV/cm CYTOP (45 nm)/SiN_(x) (50 nm) 32.2 ± 0.2 32.6 Over 3.3 MV/cm CYTOP(20 nm)/SiN_(x) (50 32.1 ± 0.2 Over 3.3 MV/cm nm)/CYTOP (20 nm) Hyflon(45 nm)/SiN_(x) (50 nm) 31.1 ± 0.3 Over 3.3 MV/cm Teflon (45 nm)/SiN_(x)(50 nm) 32.3 ± 0.2 Over 3.3 MV/cm

To prepare the OFETS, a bottom-contact and top-gate structure werefabricated on glass substrates (Corning, Eagle 2000). Au (50 nm)bottom-contact source/drain electrodes were deposited by thermalevaporation through a shadow mask. A self-assembled monolayer ofpentafluorobenzenethiol (PFBT) was formed on the Au electrodes byimmersion in a 10 mmol PFBT solution in ethanol for 15 min in aN₂-filled dry box, rinsing with pure ethanol, and drying. TheTIPS-pentacene and PTAA blend solution was prepared as follows:TIPS-pentacene and PTAA were individually dissolved in1,2,3,4-Tetrahydronaphthalene anhydrous, 99%, (Sigma Aldrich) for aconcentration of 30 mg/mL and the two individual solutions were mixed toyield a weight ratio of 1:1. TIPS-pentacene and PTAA blend active layerswere deposited by spin coating at 500 rpm for 10 sec and at 2000 rpm for20 sec. Then, samples were annealed at 100° C. for 15 min in a N₂-filleddry box. Various fluoropolymer (CYTOP, Hyflon, and Teflon)/inorganic(Al₂O₃ and SiN_(x)) bi-layers and CYTOP/inorganic (Al₂O₃ andSiN_(X))/CYTOP triple layers were used as dielectrics. CYTOP solution(CTL-809M) was purchased from Asahi Glass with a concentration of 9 wt.%. Hyflon solution (Hyflon® AD 40X) was received from Solvay, of whichconcentration is ˜6.6 wt %. Teflon solution (601S2-100-6) was purchasedfrom DuPont with a concentration of 6 wt. %. To deposit the 45-nm-thickfluoropolymer layers, the original solutions were diluted with theirsolvents (CT-solv. 180 for CYTOP, LS165 for Hyflon, and FC-40 forTeflon) to have solution:solvent ratios of 1:3.5 for CYTOP, 1:2 forHyflon, and 1:3 for Teflon. For 20 nm CYTOP layers, the solution:solventratio is 1:7. Fluoropolymer layers were deposited by spin coating at3000 (for CYTOP) and at 4000 rpm (for Hyflon, Teflon) for 60 sec. Afterdeposition, fluoropolymer layers were annealed at 100° C. for 20 min.Then, the Al₂O₃ dielectric films (50 nm) were deposited on top of thefluoropolymer layer using a Savannah 100 ALD system from CambridgeNanotech Inc. Films were fabricated at 110° C. using alternatingexposures of trimethyl aluminum [Al(CH₃)₃] and H₂O vapor at a depositionrate of approximately 0.1 nm per cycle. SiN_(x) films (50 nm) weredeposited on fluoropolymer layers by plasma enhanced chemical vapordeposition (PECVD) at 110° C. For triple layer dielectrics, CYTOP films(20 nm) deposited on the top of Al₂O₃ and SiN_(x) films and annealed at100° C. for 20 min. Finally, Al (150 nm) gate electrodes were depositedby thermal evaporation through a shadow mask.

FIGS. 24A and 24B show the transfer characteristic and outputcharacteristics for the CYTOP (45 nm)/Al₂O₃ (50 nm) bi-layer OFET. FIGS.24C and 24D show the transfer characteristic and output characteristicsfor the Hyflon (45 nm)/Al₂O₃ (50 nm) bi-layer OFET. FIGS. 24E and 24Fshow the transfer characteristic and output characteristics for theTeflon (45 nm)/Al₂O₃ (50 nm) bi-layer OFET. FIGS. 24G and 24H show thetransfer characteristic and output characteristics for the CYTOP (20nm)/Al₂O₃ (50 nm)/CYTOP (20 nm) tri-layer OFET. FIGS. 24I and 24J showthe transfer characteristic and output characteristics for the CYTOP (45nm)/S_(i)N_(x) (50 nm) bi-layer OFET. FIGS. 24K and 24L show thetransfer characteristic and output characteristics for the Hyflon (45nm)/S_(i)N_(x) (50 nm) bi-layer OFET. FIGS. 24M and 24N show thetransfer characteristic and output characteristics for the Teflon (45nm)/S_(i)N_(x) (50 nm) bi-layer OFET. FIGS. 24O and 24P show thetransfer characteristic and output characteristics for the CYTOP (20nm)/S_(i)N_(x) (50 nm)/CYTOP (20 nm) tri-layer OFET.

A summary of the performance of the tested OFETs is contained in thebelow table.

Cin Dielectric W/L (nF/cm²) μ (cm²/Vs) V_(th) (V) I_(on/off) CYTOP (40mm)/ 2550 μm/180 μm 35.2 0.98 ± 0.17 −3.7 ± 0.6 3 × 10⁴ Al₂O₃ (50 nm)(ave. 7) Hyflon (40 nm)/Al₂O₃ 2550 μm/180 μm 39.1 0.70 ± 0.09 −3.7 ± 0.210³ (50 nm) (ave. 7) Teflon (40 nm)/Al₂O₃ 2550 μm/180 μm 34.7 0.67 ±0.16 −4.1 ± 0.5 3 × 10³ (50 nm) (ave. 8) CYTOP (20 nm)/ 2550 μm/180 μm34.6 0.69 ± 0.22 −3.4 ± 0.4 5 × 10³ Al₂O₃ (50 nm)/ (ave. 7) CYTOP (20nm) CYTOP (40 nm)/SiN_(x) 2550 μm/180 μm 32.2 0.044 ± 0.025 −8.5 ± 0.410⁴ (50 nm) (ave. 8) Hyflon (40 nm)/SiN_(x) 2550 μm/180 μm 31.1 0.009 ±0.005 −8.2 ± 0.4 5 × 10³ (50 nm) (ave. 7) Teflon (40 nm)/SiN_(x) 2550μm/180 μm 32.3 0.005 ± 0.001 −6.7 ± 0.5 10³ (50 nm) (ave. 8) CYTOP (20nm)/SiN_(x) 2550 μm/180 μm 32.1 0.019 ± 0.008 −8.2 ± 0.4 10³ (50nm)/CYTOP (20 nm) (ave. 8)

It should be noted that field-effect mobility values forfluoropolymer/SiN_(x) bi-layer OFETs were 10-100 times lower than thosefor fluoropolymer/Al₂O₃ bi-layer OFETs.

Results Yielded by Other Embodiments

FIGS. 12A and 12B show the transfer and output characteristics ofamorphous InGaZnO FETs with the CYTOP (40 nm)/Al₂O₃ (50 nm) bi-layerafter multiple scans of the transfer characteristic up to 1,000 cyclesand after a constant DC bias stress for 18 hour (V_(GS)=V_(DS)=7 V).Under continuous multiple scans or under a constant DC bias stress, theoxide FET shows no degradation of mobility but a slight change in thethreshold voltage.

FIGS. 13A-13B show the transfer and output characteristics, measuredfrom pristine devices under a nitrogen atmosphere, of OFETs (W/L=2550μm/180 μm) using a CYTOP (40 nm)/Al₂O₃ (50 nm) gate dielectric and aplastic (PES) substrate, as discussed in Examiner 7. The OFETs showed nohysteresis and achieved a maximum value of μ=0.34 cm²/Vs at a lowvoltage of 8 V. Average values of the mobility μ=0.24±0.08 cm²/Vs, thethreshold voltage V_(th)=−1.3±0.1 V, I_(on)/I_(off)=10⁴ were measured inthese bi-layer devices. OFETs (W/L=2550 μm/180 μm) using a CYTOP (40nm)/Al₂O₃ (50 nm) gate dielectric and a plastic (PES) substrate wassubjected to 3600 s (1 h) of DC bias stress. FIG. 14A shows the temporalevolution of the I_(DS) measured in the OFET normalized to the initialvalue. The evolution of the CYTOP/Al₂O₃ bi-layer in the plasticsubstrate OFET was similar to that of the glass substrate device, as canbe seen by comparing FIG. 11A with FIG. 14A. FIGS. 14B and 14C show thetransfer and output characteristics of the plastic substrate OFET afterbeing subjected to the DC bias stress. FIGS. 15A and 15B show thetransfer and output characteristics of OFETs (W/L=2550 μm/180 μm) usinga CYTOP (40 nm)/Al₂O₃ (50 nm) gate dielectric and a plastic (PES)substrate initially, after 4 months in air, and after bending for 30minutes (tensile stress). FIG. 15C shows the bending apparatus used tobend the plastic substrate OFET. FIG. 15D shows the voltage transfercharacteristics of the plastic substrate OFET (determined using aresistive-load inverter) initially, after 2 hours of DC bias stress,after 4 months in air, and after bending for 30 minutes (tensilestress).

FIGS. 25A and 25B show the drain current I_(DS) with respect to gatevoltage V_(GS) for the pentacene and InGaZnO FETs discussed in Example11. FIG. 25C shows the temporal evolution of the I_(DS) measured in thepentacene and InGaZnO FETs, normalized to the initial value, under DCbias stress over 60 minutes. FIGS. 26A and 26B show the transfercharacteristics and output characteristics of the pentacene FETsdiscussed in Example 11. FIGS. 27A and 27B show the transfercharacteristics and output characteristics of the InGaZnO FETs discussedin Example 11. FIGS. 28A and 28B show the voltage transfercharacteristics and static gain of the inverter of FIG. 4G.

FIGS. 29A and 29B show the transfer characteristics and outputcharacteristics of a Polyera ActivInk N2200 based OFET with aCYTOP/Al₂O₃ bi-layer (45 nm CYTOP; 50 nm Al₂O₃) and evaporated Ausource/drain electrodes, as discussed in Example 12. FIGS. 30A and 30Bshow the transfer characteristics and output characteristics of aPolyera ActivInk N2200 based OFET with a CYTOP/Al₂O₃ bi-layer (45 nmCYTOP; 50 nm Al₂O₃) and evaporated Ag source/drain electrodes, asdiscussed in Example 13. FIGS. 31A and 31B show the transfercharacteristics and output characteristics of a Polyera ActivInk N2200based OFET with a CYTOP/Al₂O₃ bi-layer (45 nm CYTOP; 50 nm Al₂O₃) andprinted Ag source/drain electrodes, as discussed in Example 14. Asummary of the performance of the printed tested printed OFETs iscontained in the table below.

Cin compound W/L (nF/cm²) S/D electrode μ (cm²/Vs) V_(TH) (V) Ion/offP(NDI20D-T2)- 2000 μm/ 34.8 evaporated Au 0.08 0.18 2 × 103 PolyeraN2200 180 μm 2000 μm/ 34.8 evaporated Ag 0.11 0.22 8 × 103 180 μm 2000μm/ 34.8 printed Ag 0.16 1.6 3 × 103 180 μm

FIGS. 32A and 32B show the transfer characteristics and outputcharacteristics of an LEH-III-002a based OFET with a CYTOP/Al₂O₃bi-layer (45 nm CYTOP; 50 nm Al₂O₃) and Au bottom contact source/drainelectrodes in n-channel operation.

FIGS. 33A and 33B show the transfer characteristics and outputcharacteristics of an LEH-III-002a based OFET with a CYTOP/Al₂O₃bi-layer (45 nm CYTOP; 50 nm Al₂O₃) and Au bottom contact source/drainelectrodes in p-channel operation.

FIGS. 34A and 34B show the transfer characteristics and outputcharacteristics of an LEH-III-085g based OFET with a CYTOP/Al₂O₃bi-layer (45 nm CYTOP; 50 nm Al₂O₃) and Al bottom contact source/drainelectrodes.

FIGS. 35A and 35B show the transfer characteristics and outputcharacteristics of an LEH-III-085g:PαMS based OFET with a CYTOP/Al₂O₃bi-layer (45 nm CYTOP; 50 nm Al₂O₃) and Ag bottom contact source/drainelectrodes in re-channel operation.

FIGS. 36A and 36B show the transfer characteristics and outputcharacteristics of an LEH-III-085g:PαMS based OFET with a CYTOP/Al₂O₃bi-layer (45 nm CYTOP; 50 nm Al₂O₃) and Ag bottom contact source/drainelectrodes in p-channel operation.

FIGS. 37A and 37B show the results of an ambient exposure study on theLEH-III-119a based OFET with a CYTOP/Al₂O₃ bi-layer (45 nm CYTOP; 50 nmAl₂O₃) and Au bottom contact source/drain electrodes. FIG. 37A shows thetransfer characteristics of this OFET initially, after 5 days, after 17days, and after annealing. FIG. 37B shows the mobility and thresholdvoltages of this OFET initially, after 5 days, and after 17 days.

FIGS. 38A and 38B show the results of an ambient exposure study on theLEH-III-119a:PαMS based OFET with a CYTOP/Al₂O₃ bi-layer (45 nm CYTOP;50 nm Al₂O₃) and Au bottom contact source/drain electrodes. FIG. 38Ashows the transfer characteristics of this OFET initially, after 5 days,after 17 days, and after annealing. FIG. 38B shows the mobility andthreshold voltages of this OFET initially, after 5 days, and after 17days.

FIGS. 39A and 39B show the transfer characteristics and outputcharacteristics of a DRR-IV-209n based OFET with a CYTOP/Al₂O₃ bi-layer(45 nm CYTOP; 50 nm Al₂O₃).

LEH-III-002a and LEH-III-085g S/D C_(in) Batch Mode W/L electrode(nF/cm²) μ (cm²/VS) V_(TH) (V) LEH-III-002a Ambipolar 6050 μm/180 μm Au34.8  1.1 (±0.3) 13.1 (±1.1) (SPT-II-23- (n-mode) (ave. 4 dev.) C2)Ambipolar 6050 μm/180 μm Au 34.8  5.7 (±3.3) × 10⁻³ −14.4 (±0.8) (p-mode) (ave. 4 dev.) LEH-III-085g Only n- 2550 μm/180 μm Al 34.8 0.16(±0.02)  0.01 (±0.02) (SPT-II-45-a) channel (ave. 5 dev.) LEH-III-Ambipolar 6050 μm/180 μm Ag 34.8 0.72 (±0.05) 12.9 (±0.3) 085g/PaMS(n-mode) (ave. 4 dev.) blend Ambipolar 6050 μm/180 μm Ag 34.8  6.3(±1.0) × 10⁻³ −11.7 (±1.1)  (SPT-II-75-d) (p-mode) (ave. 4 dev.)

A summary of the performance of the LEH-III-002a, LEH-III-085g,LEH-III-119a, DRR-IV-209n based OFETs is shown in the tables below.

LEH-III-119a ambient stability S/D C_(in) μ Batch Ambient exposure W/Lelectrode (nF/cm²) (cm²/Vs) V_(TH) (V) LEH-III-119a Pristine 6050 μm/180μm Au 34.8 0.79 14.3 (SPT-II-57-i)  5 days in air 6050 μm/180 μm Au 34.80.67 15.1 17 days in air 6050 μm/180 μm Au 34.8 0.43 17.1 18 hrs vacuum6050 μm/180 μm Au 34.8 0.51 17.0 annealing at 100° C. LEH-III- Pristine6050 μm/180 μm Au 34.8 0.84 12.8 119a/PαMS  5 days in air 6050 μm/180 μmAu 34.8 0.55 13.8 blend (SPT-II- 17 days in air 6050 μm/180 μm Au 34.80.42 16.7 57-j) 18 hrs vacuum 6050 μm/180 μm Au 34.8 0.65 14.9 annealingat 100° C.

DRR-IV-209n Cin S/D W/L (nF/cm²) Solvent electrode μ (cm²/Vs) VTH (V)I_(on/off) 2550 μm/ 35.2 1,4-dioxane Au 0.042 ± 0.03 3.4 ± 0.5 103 180μm (ave. 9 dev.) 2550 μm/ 35.2 dichlorobenzene Au  0.13 ± 0.01 4.9 ± 0.4104 180 μm (ave. 6 dev.)

In conclusion, the multilayer approach of the invention opens up theopportunity to develop environmentally and operationally stable OFETsfor many applications. Examples of such applications include: driversfor information displays and medical imaging arrays, complementarycircuits, adaptive solar cell arrays, radio-frequency identification(RFID) tags, and chemical or physical sensors among many others. Inapplications such as active matrix display backplanes, where a constantcurrent supply is required, bias stress effects have a detrimentalimpact over the display performance. For such applications theembodiment of the invention will have substantial advantages over forinstance, current amorphous silicon (a-Si) FET technologies which arevery susceptible to bias stress effects. A particularly attractiveapplication of the invention refers to backplane circuits of activematrix organic light emitting diode (AMOLED) displays for commercialuse. This is because conventional AMOLED displays need more transistorsto compensate variations of the threshold voltage and mobility due tothe degradation of driving transistor to prevent non-uniformity oforganic light-emitting diode. This invention will allow high integrationdensity and excellent backplane stability to operate AMOLED displays.

While the principles of the invention have been set out above inconnection with specific embodiments, it is to be clearly understoodthat this description is merely made by way of example and not as alimitation of the scope of protection which is determined by theappended claims.

1. A field-effect transistor comprising: a gate, a source and a drain; asemiconductor layer between said source and said drain; and a gateinsulator between said gate and said semiconductor layer; wherein saidgate insulator comprises: a first layer adjoining said semiconductorlayer; and a second layer; said first layer formed from an fluoropolymerhaving a first dielectric constant and a first thickness; said secondlayer having a second dielectric constant and a second thickness, saidfirst dielectric constant being smaller than 3, said first thicknessbeing smaller than 200 nm, said second dielectric constant being higherthan 5, and said second thickness being smaller than 500 nm. 2.(canceled)
 3. The field-effect transistor of claim 1, wherein thefluoropolymer is an amorphous fluoropolymer that has a glass transitiontemperature above 80 degrees Celcius and is selected from the groupconsisting of a copolymer of: fluorinated 1,3-dioxole andtetrafluoroethylene (TFE), a copolymer of perfluorofuran (PFF) andtetrafluoroethylene (TFE), a homo- or copolymer ofperfluoro(4-vinyloxyl)-1-alkenes, and combinations thereof. 4-6.(canceled)
 7. The field-effect transistor of claim 3, wherein the secondlayer is formed from an inorganic material, said inorganic materialbeing Al₂O₃. 8-11. (canceled)
 12. The field-effect transistor of claim1, wherein the semiconductor layer comprises a material having thestructure:

or a blend of this material with poly(α-methyl styrene) (PαMS). 13-14.(canceled)
 15. A field-effect transistor comprising: a gate, a sourceand a drain; a semiconductor layer between said source and said drain;and a gate insulator between said gate and said semiconductor layer;wherein said gate insulator comprises: a first layer adjoining saidsemiconductor layer at an interface; and a second layer; said firstlayer having a first dielectric constant and a first thickness; saidinterface comprising a plurality of traps causing a first effect on acurrent between the drain and the source over time under continuous biasstress; said second layer having a second dielectric constant and asecond thickness, said second dielectric constant being higher than saidfirst dielectric constant, said second layer being arranged such thatsaid second dielectric constant increases over time under continuousbias stress causing a second effect on the current between the drain andthe source over time under continuous bias stress; wherein said firstand second thickness and said first and second dielectric constant aresuch that said first effect compensates at least partly said secondeffect.
 16. The field-effect transistor of claim 15, wherein said secondlayer comprises dipoles causing an increase of the second dielectricconstant over time under continuous bias stress. 17-20. (canceled) 21.The field-effect transistor of claim 15, wherein the first layer isformed of a copolymer of4,5-difluoro-2,2-bis(trifluoromethyl)-1,3-dioxole (PDD) andtetrafluoroethylene (TFE), or a copolymer of2,2,4-trifluoro-5-trifluoromethoxy-1,3-dioxole (TTD) andtetrafluoroethylene (TFE).
 22. (canceled)
 23. The field-effecttransistor of claim 21, wherein optionally the material of the secondlayer is Al₂O₃, and wherein the second layer is deposited by atomiclayer deposition (ALD).
 24. (canceled)
 25. The field-effect transistorof claim 15, wherein the thickness of the first layer is less than 200nm and the thickness of the second layer is less than 500 nm. 26-34.(canceled)
 35. A process for manufacturing a top gate field effecttransistor, the process comprising: providing a source, a drain, a gate,a semiconductor layer between the source and the drain, and a gateinsulator between said gate and said semiconductor layer; whereinproviding said gate insulator comprises: depositing a first layer havinga first dielectric constant and a first thickness, said first layerdefining an interface with said semiconductor layer; wherein thedepositing of said first layer is such that said interface comprises aplurality of traps causing a first effect on the drain source currentover time under continuous bias stress; and depositing a second layerhaving a second dielectric constant and a second thickness, said seconddielectric constant being higher than said first dielectric constant andsaid second dielectric constant increasing over time under continuousbias stress causing a second effect on the drain source current overtime under continuous bias stress; wherein said first and secondthickness and said first and second dielectric constant are chosen insuch a way that said first effect compensates at least partly saidsecond effect. 36-39. (canceled)
 40. The field-effect transistor ofclaim 1, wherein the second layer is deposited by atomic layerdeposition.
 41. The field-effect transistor of claim 40, wherein thesecond layer has a thickness of less than 100 nm.
 42. The field-effecttransistor of claim 40, wherein the second layer is an Al₂O₃ layer. 43.The field-effect transistor of claim 42, wherein the Al₂O₃ layer isgrown using alternating exposures of trimethyl aluminum (Al(CH₃)₃) andH₂O vapor.
 44. The field-effect transistor of claim 15, wherein thesecond layer is deposited by atomic layer deposition.
 45. Thefield-effect transistor of claim 44, wherein the second layer has athickness of less than 100 nm.
 46. The field-effect transistor of claim44, wherein the second layer is an Al₂O₃ layer.
 47. The processaccording to claim 35, wherein the second layer is deposited by atomiclayer deposition.
 48. The process of claim 47, wherein the second layeris an Al₂O₃ layer having a thickness of less than 100 nm.
 49. Theprocess of claim 48, wherein the Al₂O₃ layer is grown using alternatingexposures of trimethyl aluminum (Al(CH₃)₃) and H₂O vapor.